A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

A physical quantity sensor includes a substrate, a movable section displaceable in a first direction with respect to the substrate, first and second movable electrode sections provided in the movable section, a first fixed electrode section fixed to the substrate and disposed to be opposed to the first movable electrode section in the first direction, a second fixed electrode section fixed to the substrate and disposed to be opposed to the second movable electrode section in the first direction, a restricting section configured to restrict a movable range in the first direction of the movable section, a first wire provided on the substrate and electrically connected to the first fixed electrode section, and a second wire provided on the substrate and electrically connected to the second fixed electrode section. The first wire and the second wire are respectively cross the restricting section in a plan view of the substrate.

Provided are a chip packaging method and a chip packaging structure. The passivation layer is arranged on the pads of the wafer, then the first bonding layer is formed on the passivation layer, and the second bonding layer is formed on the substrate. The substrate and the wafer are bonded and packaged together by bonding the first bonding layer and the second bonding layer. The pads are only used as a conductive structure, not as a bonding layer due to the passivation layer arranged between the pads and the bonding layer. The through silicon via is arranged at the position above the pad and avoiding the bonding layer, so as to connect the functional circuit region between the wafer and the substrate to the outside of the chip packaging structure.

Provided are a chip packaging method and a chip packaging structure. The passivation layer is arranged on the pads of the wafer, then the first bonding layer is formed on the passivation layer, and the second bonding layer is formed on the substrate. The substrate and the wafer are bonded and packaged together by bonding the first bonding layer and the second bonding layer. The pads are only used as a conductive structure, not as a bonding layer due to the passivation layer arranged between the pads and the bonding layer. The through silicon via is arranged at the position above the pad and avoiding the bonding layer, so as to connect the functional circuit region between the wafer and the substrate to the outside of the chip packaging structure.

A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.

A sensor package including a fixed frame, a moveable platform, elastic restoring members and a sensor chip is provided. The moveable platform is moved with respect to the fixed frame, and used to carry the sensor chip. The elastic restoring members are connected between the fixed frame and the moveable platform, and used to restore the moved moveable platform to an original position. The sensor chip is arranged on the elastic restoring members to send detected data via the elastic restoring members.

An electronic device includes a package substrate, a circuit assembly, and a housing. The circuit assembly is mounted on the package substrate. The circuit assembly includes a first sealed cavity formed in a device substrate. The housing is mounted on the package substrate to form a second sealed cavity about the circuit assembly.

A thin-film package includes: a substrate; a wiring layer disposed on the substrate; a microelectromechanical systems (MEMS) element disposed on a surface of the substrate; a partition wall disposed on the substrate to surround the MEMS element, and formed of a polymer material; a cap forming a cavity with the substrate and the partition wall; and an external connection electrode connected to the wiring layer. The external connection electrode includes at least one inclined portion disposed on at least one inclined surface formed on any one or any combination of any two or more of the substrate, the partition wall, and the cap.

In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.