Patent classifications
B81B2207/097
Microelectromechanical device with signal routing through a protective cap
A microelectromechanical device includes: a body accommodating a microelectromechanical structure; and a cap bonded to the body and electrically coupled to the microelectromechanical structure through conductive bonding regions. The cap including a selection module, which has first selection terminals coupled to the microelectromechanical structure, second selection terminals, and at least one control terminal, and which can be controlled through the control terminal to couple the second selection terminals to respective first selection terminals according, selectively, to one of a plurality of coupling configurations corresponding to respective operating conditions.
Packaging a sealed cavity in an electronic device
An electronic device includes a package substrate, a circuit assembly, and a housing. The circuit assembly is mounted on the package substrate. The circuit assembly includes a first sealed cavity formed in a device substrate. The housing is mounted on the package substrate to form a second sealed cavity about the circuit assembly.
Sensor package having a movable sensor
A sensor package including a fixed frame, a moveable platform, elastic restoring members and a sensor chip is provided. The moveable platform is moved with respect to the fixed frame, and used to carry the sensor chip. The elastic restoring members are connected between the fixed frame and the moveable platform, and used to restore the moved moveable platform to an original position. The sensor chip is arranged on the elastic restoring members to send detected data via the elastic restoring members.
MEMS CHIP AND ELECTRICAL PACKAGING METHOD FOR MEMS CHIP
Embodiments of the application provide a MEMS chip and an electrical packaging method for a MEMS chip. The MEMS chip includes a MEMS device layer, a first isolating layer located under the MEMS device layer, and a first conducting layer located under the first isolating layer. At the first isolating layer, there are a corresponding quantity of first conductive through holes in locations corresponding to conductive structures in a first region and in locations corresponding to electrodes in a second region. At the first conducting layer, there are M electrodes spaced apart from one another, and the M electrodes are respectively connected to M of the first conductive through holes. At the first conducting layer, electrodes in locations corresponding to at least some of the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to at least some of the electrodes in the second region.
Sensor component having two sensor functions
A sensor component having a MEMS sensor and an ASIC for one sensor function each. A base element, a wall element in the form of a frame and a cover together enclose a cavity of a housing. The MEMS sensor is mounted inside the cavity on the base element of the housing. The ASIC has an active sensor surface and is mounted on or under the cover or is embedded in the cover. Electrical external contacts for the MEMS sensor and ASIC are provided on an external surface of the housing. The cavity has at least one opening or bushing.
Nickel lanthanide alloys for mems packaging applications
A semiconductor package including a semiconductor die and at least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy diffusion barrier layer abutting a gold layer.
NICKEL LANTHANIDE ALLOYS FOR MEMS PACKAGING APPLICATIONS
A semiconductor package including a semiconductor die and at least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy diffusion barrier layer abutting a gold layer.
MEMS Structure with Reduced Peeling and Methods Forming the Same
A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.
Bonded structures
A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.
ELECTRONIC COMPONENT WITH REDUCED STRESS
A packaging arrangement is provided that suppresses stress induced by extreme temperature changes during the process of attaching the electronic component. The arrangement includes adding to the package columnar conductors embedded in a solid support substance.