B81C1/00031

MODIFICATION TO ROUGH POLYSILICON USING ION IMPLANTATION AND SILICIDE
20220144628 · 2022-05-12 ·

A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.

COMB ELECTRODE RELEASE PROCESS FOR MEMS STRUCTURE
20230249964 · 2023-08-10 ·

An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger has a second height less than the first height.

COMB ELECTRODE RELEASE PROCESS FOR MEMS STRUCTURE
20220119247 · 2022-04-21 ·

An integrated circuit (IC) device includes: a first substrate; a dielectric layer disposed over the first substrate; and a second substrate disposed over the dielectric layer. The second substrate includes anchor regions comprising silicon extending upwards from the dielectric layer, and a series of interdigitated fingers extend from inner sidewalls of the anchor regions. The interdigitated fingers extend generally in parallel with one another in a first direction and have respective finger lengths that extend generally in the first direction. A plurality of peaks comprising silicon is disposed on the dielectric layer directly below the respective interdigitated fingers. The series of interdigitated fingers are cantilevered over the plurality of peaks. A first peak is disposed below a base of a finger and has a first height, and a second peak is disposed below a tip of the finger and has a second height less than the first height.

Laminate For Patterned Substrates

The present application relates to a block copolymer and a use thereof. The present application can provide a laminate which is capable of forming a highly aligned block copolymer on a substrate and thus can be effectively applied to production of various patterned substrates, and a method for producing a patterned substrate using the same.

Structured grating component, imaging system and manufacturing method

The invention relates to a method of manufacturing a structured grating, a corresponding structured grating component (1) and an imaging system. The method comprising the steps of: providing (110, 120, 130) a catalyst (30) on a substrate (20), the catalyst (20) having a grating pattern; growing (140) nanostructures (50) on the catalyst (30) so as to form walls (52) and trenches (54) based on the grating pattern; and filling (160) the trenches (54) between the walls (52) of nanostructures (50) using an X-ray absorbing material (70). The invention provides an improved method for manufacturing a structured grating and such structured grating component (1), which is particularly suitable for dark-field X-ray imaging or phase-contrast imaging.

Method and device for a carrier proximity mask

A carrier proximity mask and methods of assembling and using the carrier proximity mask may include providing a first carrier body, second carrier body, and set of one or more clamps. The first carrier body may have one or more openings formed as proximity masks to form structures on a first side of a substrate. The first and second carrier bodies may have one or more contact areas to align with one or more contact areas on a first and second sides of the substrate. The set of one or more clamps may clamp the substrate between the first carrier body and the second carrier body at contact areas to suspend work areas of the substrate between the first and second carrier bodies. The openings to define edges to convolve beams to form structures on the substrate.

Nanowire-coated microdevice and method of making and using the same

A microdevice containing a plurality of nanowires on a biocompatible surface, and methods of making and using the same are provided. Aspects of the present disclosure include forming a plurality of microdevices on a substrate where each microdevice includes a plurality of nanowires. The nanowires may be loaded with an active agent by disposing the active agent onto the surface of the nanowires. Also provided herein are kits that include the subject microdevices.

Laminate for patterned substrates

The present application relates to a block copolymer and a use thereof. The present application can provide a laminate which is capable of forming a highly aligned block copolymer on a substrate and thus can be effectively applied to production of various patterned substrates, and a method for producing a patterned substrate using the same.

Methods for forming flow channels in metal inverse opal structures

A method for forming a flow channel in a MIO structure includes positioning a plurality of sacrificial spheres along a base substrate, heating a region of the plurality of sacrificial spheres above a melting point of the plurality of sacrificial spheres, thereby fusing the plurality of sacrificial spheres together and forming a solid channel, electrodepositing material between the plurality of sacrificial spheres and around the solid channel, removing the plurality of sacrificial spheres to form the MIO structure, and removing the solid channel to form the flow channel extending through the MIO structure.

Hierarchical Silicon Nanostructures, Methods of Making, and Methods of Use
20230312336 · 2023-10-05 ·

Described herein are antireflective materials and methods of making antireflective materials. The material can include a plurality of hierarchical nanostructures on abase substrate and a total specular reflection of less than 3% at a wavelength of about 400 nm to about 1100 nm. The material can have an etched polyimide layer disposed on the superior surface of the hierarchical nanostructures. The materials can also have superhydrophobic characteristics.