Patent classifications
B81C1/00087
Self-limited, anisotropic wet etching of transverse vias in microfluidic chips
The present invention is notably directed to a method of fabrication of a microfluidic chip (1), comprising: providing (S10-S20) a wafer (10, 12) of semiconductor material having a diamond cubic crystal structure, exhibiting two opposite main surfaces (S1, S2), one on each side of the wafer, and having, each, a normal in the <100> or <110> direction; and performing (S30) self-limited, anisotropic wet etching steps on each of the two main surfaces on each side of the wafer, to create a via (20, 20a) extending transversely through the thickness of the wafer, at a location such that the resulting via connects an in-plane microchannel (31) on a first one (S1) of the two main surfaces to a second one (S2) of the two main surfaces, the via exhibiting slanted sidewalls (20s) as a result of the self-limited wet etching. The invention further concerns microfluidic chips accordingly obtained.
COMPONENT BASED ON A STRUCTURABLE SUBSTRATE WITH A MEMBRANE STRUCTURE HAVING THREE-DIMENSIONAL PORES IN THE NM RANGE AND SEMICONDUCTOR TECHNOLOGY METHOD FOR MANUFACTURING SAME
The invention relates to a component, comprising a carrier made of a structurable material with at least one continues opening which is closed by a porous membrane, characterized in that the porous membrane protrudes from the surface of the component surrounding the continuous opening. In some embodiments, the component further comprises a carrier substrate, wherein a side of the carrier substrate which faces the component and the opposite side of the component preferably form a fluid channel, wherein the at least one continuous opening of the carrier preferably communicates on its open side with the fluid channel. The component according to the invention is suitable for the installation and electrochemical measuring of transmembrane proteins, preferably in lipid bilayers. The invention also proposes different methods for producing the component.
METHOD FOR WET ETCHING OF BLOCK COPOLYMER SELF-ASSEMBLY PATTERN
The present invention relates to a process for selectively removing a block on one side using a wet etching process in connection with self-assembly block copolymer thin films that have etching-resisting properties different from each other. The present invention can form a vertical nanopore structure having a high aspect ratio, even in the case of a thick film which has a vertically oriented cylinder self-assembly structure and which has one or more periods, by overcoming the limit of the prior art, which cannot implement a vertical pore structure through wet etching.
DNA SEQUENCING WITH STACKED NANOPORES
A sensing device includes a stack of dielectric layers having conductive materials disposed between the dielectric layers. A nanopore is disposed through the stacks of dielectric layers and separates the conductive materials to provide electrodes on opposite sides of the nanopore. Contacts connect to each of the electrodes.
METHOD FOR PROCESSING SILICON SUBSTRATE AND METHOD FOR PROCESSING LIQUID EJECTION HEAD SUBSTRATE
A method for processing a silicon substrate is provided the method including repeatedly and alternately performing: an etching step of forming an etching pattern on the silicon substrate; and a protective film formation step of forming a protective film on a wall surface of the silicon substrate exposed in the etching step, wherein the method includes a protective film removal step of removing the protective film, which has been formed in the protective film formation step, by using a peeling solution, and wherein in the protective film formation step, the protective film is formed by using a mixed gas including 2,3,3,3-tetrafluoropropene and perfluorocyclobutane.
Nanogap structure for micro/nanofluidic systems formed by sacrificial sidewalls
A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.
Fabrication of nanopores using high electric fields
A method is provided for fabricating a nanopore in a membrane. The method includes: applying an electric potential across the membrane, where value of the electric potential is selected to induce an electric field which causes a leakage current across the membrane; monitoring current flow across the membrane while the electric potential is being applied; detecting an abrupt increase in the leakage current across the membrane; and removing the electric potential across the membrane in response to detecting the abrupt increase in the leakage current.
Method Of Manufacturing A Plurality Of Through-Holes In A Layer Of First Material
A method of manufacturing a plurality of through-holes in a layer of first material by subjecting part of the layer of said first material to ion beam milling.
For batch-wise production, the method comprises after a step of providing the layer of first material and before the step of ion beam milling, providing a second layer of a second material on the layer of first material, providing the second layer of the second material with a plurality of holes, the holes being provided at central locations of pits in the first layer, and subjecting the second layer of the second material to said step of ion beam milling at an angle using said second layer of the second material as a shadow mask.
INTEGRATION OF LAMINATE MEMS IN BBUL CORELESS PACKAGE
An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.
MEMS pressure sensor and method of manufacturing the same
A micro-electro mechanical system (MEMS) pressure sensor includes a first substrate, a second substrate and a sensing structure. The second substrate is substantially parallel to the first substrate. The sensing structure is between the first substrate and the second substrate, and bonded to a portion of the first substrate and a portion of the second substrate, in which a first space between the first substrate and the sensing structure is communicated with outside, and a second space between the second substrate and the sensing structure is communicated with or isolated from the outside.