The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.

The present invention provides a new architecture of system-on-chip ultrasonic transducer array. It is based on fusion bond of two active wafers which have prefabricated CMOS integrated circuits and CMUT structures; precise thin-down of one wafer to form CMUT monocrystalline silicon membrane; and then to vertically connect CMUT array to CMOS IC layers underneath. This architecture can realize a high-density CMUT array with multiple layers of CMOS devices, such as all supporting CMOS ICs, to achieve a SOC solution. The present invention further provides a manufacturing method for above-mentioned SOC CMUT approach, and this manufacturing process can be realized in both 8 inch and 12-inch wafer manufacturing fabs. The disclosed manufacturing processes are more compatible with existing CMOS process flow, more cost-competitive for mass production.

A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

A sensor device includes a first and second Micro-Electro-Mechanical (MEM) structures. The first MEM structure includes a first heating element on a first layer of the first MEM structure. The first heating element includes an input adapted to receive an input signal. The first MEM structure also includes a first temperature sensing element on a second layer of the first MEM structure. The second MEM structure includes a second heating element on a first layer of the second MEM structure and a second temperature sensing element on a second layer of the second MEM structure. An output circuit has a first input coupled to the first temperature sensing element and a second input coupled to the second temperature sensing element.

A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.

A micromechanical sensor device and a corresponding manufacturing method are described. The micromechanical sensor device is fitted with a substrate including a front side and a rear side; a micromechanical sensor chip including a sensor area attached to the front side of the substrate; and a capping unit attached to the front side of the substrate, which is formed at least partially by an ASIC chip. The capping unit surrounds the micromechanical sensor chip in such a way that a cavity closed toward the front side of the substrate is formed between the sensor area of the micromechanical sensor chip and the ASIC chip. A mold package is formed above the capping unit.

A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.