A method includes obtaining an active device layer. The active device layer has a first surface with one or more active feature areas. First portions of the active feature areas are exposed, and second portions of the active feature areas are covered by an insulating layer. A conformal overcoat layer is formed on the first surface. A base of a microelectromechanical systems (MEMS) device layer is formed on the conformal overcoat layer. The MEMS device layer is spatially segregated from the active feature areas by removing portions of the base of the MEMS device layer in one or more antiparasitic regions (APRs) that correspond to the active feature areas. Metal MEMS features are formed on the base of the MEMS device layer. Selected portions of the active feature areas are exposed removing portions of the conformal overcoat layer that overlay the active feature areas.

Aspects of the invention relate to a semiconductor chip comprising a substrate and a stack arranged on the substrate. The stack comprises one or more insulating layers and one or more metal layers. The chip comprises a sensor device arranged in a sensor area (SA) of the semiconductor chip and processing circuitry arranged in a processing area (PA) of the semiconductor chip. The chip further comprises connection circuitry configured to provide an electrical connection between the sensor device and the processing circuitry. A first seal ring structure is arranged between an outer edge (ED) of the chip and an inner area (IA) of the chip. The inner area (IA) of the chip encompasses the sensor area (SA) and the processing area (PA). A second seal ring structure is arranged between the sensor area (SA) and the processing area (PA) and configured to constrain an infiltration of contaminants from the sensor area (SA) to the processing area (PA).

A CMOS-based sensing device includes a substrate including an etched portion and a first region located on the substrate. The first region includes a membrane region formed over an area of the etched portion of the substrate, a flow sensor formed within the membrane region and a pressure sensor formed within the membrane region.

An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

The disclosure relates to a microelectromechanical apparatus including a substrate, a stationary electrode, a movable electrode, and a heater. The substrate includes an upper surface, an inner bottom surface, and an inner side surface. The inner side surface surrounds and connects with the inner bottom surface. The inner side surface and the inner bottom surface define a recess. The stationary electrode is disposed on the inner bottom surface. The movable electrode covers the recess. The movable electrode, the inner bottom surface, and the inner side surface define a hermetic chamber. The heater is disposed on the movable electrode and located above the hermetic chamber.

A monolithic integrated device may include a first device having a complementary metal-oxide-semiconductor (CMOS) substrate, and a second device arranged over the CMOS substrate. The second device may include a first conductive element, and a second conductive element arranged over the first conductive element. A via opening may extend through the first conductive element and the second conductive element of the second device to an interconnect of the CMOS substrate. A via contact may be arranged in the via opening to contact the first conductive element, the second conductive element, and the interconnect of the CMOS substrate. The via contact electrically connects the first conductive element and the second conductive element of the second device to the interconnect of the CMOS substrate.

An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.

Methods for forming an electrode structure, which can be used as a biosensor, are provided in which the electrode structure has non-random topography located on one surface of an electrode base. In some embodiments, an electrode structure is obtained that contains no interface between the non-random topography of the electrode structure and the electrode base of the electrode structure. In other embodiments, electrode structures are obtained that have an interface between the non-random topography of the electrode structure and the electrode base of the electrode structure.

A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermoconforms. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.