A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.

Microelectromechanical (MEMS) devices and associated methods are disclosed. Piezoelectric MEMS transducers (PMUTs) suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuit (IC), as well as PMUT arrays having high fill factor for fingerprint sensing, are described.

A complementary metal-oxide-semiconductor (CMOS) micro electro-mechanical system (MEMS) microphone and a method for fabricating the same are disclosed. Firstly, a CMOS device including a semiconductor substrate, a first oxide insulation layer, a doped polysilicon layer, a second oxide insulation layer, a patterned polysilicon layer, and a metal wiring layer from bottom to top. The metal wiring layer is formed on the second oxide insulation layer. The patterned polysilicon layer includes undoped polysilicon. Then, a part of the metal wiring layer is removed to form a metal electrode and the semiconductor substrate is penetrated to have a chamber and expose the first oxide insulation layer, thereby forming a MEMS microphone.

An ultrasonic transducer includes a membrane, a bottom electrode, and a plurality of cavities disposed between the membrane and the bottom electrode, each of the plurality of cavities corresponding to an individual transducer cell. Portions of the bottom electrode corresponding to each individual transducer cell are electrically isolated from one another. Each portion of the bottom electrode corresponds to each individual transducer that cell further includes a first bottom electrode portion and a second bottom electrode portion, the first and second bottom electrode portions electrically isolated from one another.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition. A second functional structure overlies the second movable membrane, where the second functional structure is laterally spaced from the first functional structure, and where the second functional structure comprises a second material having a second chemical composition different than the first chemical composition.

A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

A CMOS single chip includes a movable film, at least one support pillar, a base metal layer and a circuit integration. The movable film is disposed on a top layer of the CMOS single chip and has a plurality of through-vias. The support pillar is disposed under the movable film to provide a supporting force of the movable film. The base metal layer is formed under the support pillars and isolated from the support pillars, and faces towards the movable film to form a micro capacitor to sense one of the outside sensing signals. The area of the base metal layer is larger than the area of the movable film. The circuit integration is formed under the base metal layer, or formed under the base metal layer and on the side of the movable film, and connected to the movable film and the base metal layer.

An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

Device and method of forming a device are disclosed. The device includes a substrate with a transistor component disposed in a transistor region and a micro-electrical mechanical system (MEMS) component disposed on a membrane over a lower sensor cavity in a hybrid region. The MEMS component serves as thermoelectric-based infrared sensor, a thermopile line structure which includes an absorber layer disposed over a portion of oppositely doped first and second line segments. A back-end-of-line (BEOL) dielectric is disposed on the substrate having a plurality of inter layer dielectric (ILD) layers with metal and via levels. The ILD layers include metal lines and via contacts for interconnecting the components of the device. The metal lines in the metal levels are configured to define a BEOL or an upper sensor cavity over the lower sensor cavity, and metal lines of a first metal level of the BEOL dielectric are configured to define a geometry of the MEMS component.

A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermosensors. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.