Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition. A second functional structure overlies the second movable membrane, where the second functional structure is laterally spaced from the first functional structure, and where the second functional structure comprises a second material having a second chemical composition different than the first chemical composition.

A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.

An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole.

A system for molecular mapping includes a semiconductor substrate defining a reservoir to receive a sample of molecules and a nanofluidic channel in fluid communication with the reservoir. The system also includes a plurality of electrodes, in electrical communication with the nanofluidic channel, to electrophoretically trap the sample of molecules in the nanofluidic channel. At least one avalanche photodiode is fabricated in the semiconductor substrate and disposed within an optical near-field of the nanofluidic channel to detect fluorescence emission from at least one molecule in the sample of molecules.

To implement a single-chip ultrasonic imaging solution, on-chip signal processing may be employed in the receive signal path to reduce data bandwidth and a high-speed serial data module may be used to move data for all received channels off-chip as digital data stream. The digitization of received signals on-chip allows advanced digital signal processing to be performed on-chip, and thus permits the full integration of an entire ultrasonic imaging system on a single semiconductor substrate. Various novel waveform generation techniques, transducer configuration and biasing methodologies, etc., are likewise disclosed. HIFU methods may additionally or alternatively be employed as a component of the ultrasound-on-a-chip solution disclosed herein.

Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.

A MEMS device includes, in part, first and second conductive semiconductor substrates, an insulating material disposed between the semiconductor substrates, a cavity formed in the second semiconductor substrate, and at least first and second drive masses each of which includes a multitude of beams etched from the first semiconductor substrate and is adapted to move in the cavity in response to an applied force. At least a first portion of the first substrate is adapted to move in response to the applied force and causes the at least first and second drive mass to be in electrical communication with the first substrate. The device may further include, in part, a coupling spring disposed between and in electrical communication with the first and second drive masses. The coupling spring is adapted to provide electrical communication between a second portion of the first substrate and the first and second drive masses.

A micromechanical apparatus and a corresponding production method are described. The micromechanical apparatus encompasses a base substrate having a front side and a rear side; and a cap substrate, at least one surrounding trench having non-flat side walls being embodied in the front side of the base substrate; the front side of the base substrate and the trench being coated with at least one metal layer; the non-flat side walls of the trench being covered nonconformingly with the metal so that they do not form an electrical current path in a direction extending perpendicularly to the front side; and a closure, in particular a seal-glass closure, being embodied in the region of the trench between the base substrate and the cap substrate.

An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.