A semiconductor device comprises a first doped semiconductor layer, a second doped semiconductor layer, an oxide layer covering the first doped semiconductor layer and the second doped semiconductor layer, and an interconnect. The first doped semiconductor layer is electrically connected with the second doped semiconductor layer by means of the interconnect which crosses over a sidewall of the second doped semiconductor layer. The interconnect comprises a metal filled slit in the oxide layer. At least one electronic component is formed in the first and/or second semiconductor layer. The semiconductor device moreover comprises a passivation layer which covers the first and second doped semiconductor layers and the oxide layer.

A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device monolithically after CMOS processing. For example, the MEMS sensors are formed over a BEOL dielectric of a CMOS device. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region.

The invention relates to antenna apparatus comprising: an antenna, a signal conductor and one or more RF MEMS switches, the antenna being conductively connected to the signal conductor, the MEMS switches and at least a portion of the signal conductor being supported by a crystalline MEMS substrate; and a capping substrate comprising a capping portion, wherein an enclosed volume is formed around the said MEMS switches between the capping portion and at least a portion of the crystalline MEMS substrate, and wherein the capping substrate comprises the said antenna.

A micro-electro-mechanical device, comprising a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region facing the first buried cavity; a second cavity facing the first buried cavity; a decoupling trench extending from the monolithic body and separating the sensitive region from a peripheral portion of the monolithic body; a cap die, forming an ASIC, bonded to and facing the first face of the monolithic body; and a first gap between the cap die and the monolithic body. The device also comprises at least one spacer element between the monolithic body and the cap die; at least one stopper element between the monolithic body and the cap die; and a second gap between the stopper element and one between the monolithic body and the cap die. The second gap is smaller than the first gap.

Microelectromechanical (MEMS) devices and associated methods are disclosed. Piezoelectric MEMS transducers (PMUTs) suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuit (IC), as well as PMUT arrays having high fill factor for fingerprint sensing, are described.

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.

According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein.

To implement a single-chip ultrasonic imaging solution, on-chip signal processing may be employed in the receive signal path to reduce data bandwidth and a high-speed serial data module may be used to move data for all received channels off-chip as digital data stream. The digitization of received signals on-chip allows advanced digital signal processing to be performed on-chip, and thus permits the full integration of an entire ultrasonic imaging system on a single semiconductor substrate. Various novel waveform generation techniques, transducer configuration and biasing methodologies, etc., are likewise disclosed. HIFU methods may additionally or alternatively be employed as a component of the “ultrasound-on-a-chip” solution disclosed herein.

Ultrasonic sensing approaches are described with integrated MEMS-CMOS implementations. Embodiments include ultrasonic sensor arrays for which PMUT structures of individual detector elements are at least partially integrated into the CMOS ASIC wafer. MEMS heating elements are integrated with the PMUT structures by integrating under the PMUT structures in the CMOS wafer and/or over the PMUT structures (e.g., in the protective layer). For example, embodiments can avoid wafer bonding and can reduce other post processing involved with conventional manufacturing of PMUT ultrasonic sensors, while also improving thermal response.