A through substrate via is formed by disposing a quantity of solder material at the top of a through hole formed in a substrate, coating the hole with a wetting layer, and melting the solder material such that it flows into the hole. The solder material may alloy with the wetting layer, freezing upon formation of the alloy. Subsequent processing steps may be performed at temperatures higher than the melting point of the solder material.

A component which can be produced at wafer level has a first chip and a second chip connected thereto. The connection is (at least partially) established via a first and a second connecting structure and a first and a second contact structure of the second chip. An adaptation structure between the first chip and the first connecting structure equalizes a height difference between the first and the second contact structure.

A device includes a base substrate (700) with a micro component (702) attached thereto. Suitably it is provided with routing elements (704) for conducting signals to and from the component (702). It also includes spacer members (706) which also can act as conducting structures for routing signals vertically. There is a capping structure (708) of a glass material, provided above the base substrate (700), bonded via the spacer members (706), preferably by eutectic bonding, wherein the capping structure (708) includes vias (710) including metal for providing electrical connection through the capping structure. The vias can be made by a stamping/pressing method entailing pressing needles under heating to soften the glass and applying pressure, to a predetermined depth in the glass. However, other methods are possible, e-g- drilling, etching, blasting.

The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

A method includes placing a microelectromechanical system (MEMS) device over a carrier, wire bonding the MEMS device to a bond pad on the carrier with a bond wire, and spray coating a buffer layer over the MEMS device and enclosing the bond wire. A Young's modulus value of the buffer layer is less than a Young's modulus value of the MEMS device.

A hermetically sealed component may comprise a glass substrate, a device with at least one electrical port associated with the glass substrate, and a glass cap. The glass cap may have at least one side wall. The glass cap may have a shaped void extending therethrough, from top surface of the glass cap to bottom surface of glass pillar. An electrically conductive plug may be disposed within the void, the plug configured to hermetically seal the void. The electrically conductive plug may be electrically coupled to the electrical port. The glass cap may be disposed on the glass substrate, with the at least one side wall disposed therebetween, to form a cavity encompassing the device. The side wall may contact the glass substrate and the glass cap to provide a hermetic seal, such that a first environment within the cavity is isolated from a second environment external to the cavity.

A resonance device that includes a MEMS substrate that includes a resonator, a top cover having a silicon oxide film on a surface thereof that faces the MEMS substrate, and a bonding part that bonds the MEMS substrate and the top cover to each other so as to seal a vibration space of the resonator. The silicon oxide film includes a through hole that is formed along at least part of the periphery of the vibration space when the top cover is viewed in a plan view and that penetrates to a surface of the top cover. The through hole includes a first metal layer.

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

Substrate is produced by using a MEMS technique to form multiple diaphragms in a substrate by forming piezoelectric material layer on one surface of the substrate and thereafter by forming openings in the substrate from the other surface of the substrate; substrate and substrate on which signal detection circuit is formed are aligned to each other using at least one of multiple diaphragms as alignment diaphragm; and substrate and substrate are bonded together.