A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

A method of manufacturing a dielectric barrier discharge (DBD) structure includes forming a patterned electrode layer around an outer perimeter of a substrate composed of a dielectric material. The patterned electrode layer includes multiple electrodes around the outer perimeter of the substrate and gaps between adjacent electrodes. The method further includes depositing a dielectric layer over at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.

A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

A method for producing a semiconductor component is proposed. The method includes providing a housing. At least one semiconductor chip is arranged in a cavity of the housing. Furthermore, an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire. The method furthermore includes applying a protective material on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing. Moreover, the method also includes filling at least one partial region of the cavity with a gel.

Certain embodiments of the present disclosure relate to a sensor assembly including a substrate having an outer region, an inner region, and a middle region between the outer region and the inner region. The substrate further includes electrical contact pads on at least the inner region. The sensor assembly further includes a housing coupled to the substrate at the middle region or the outer region to provide a hermetic seal. The sensor assembly further includes a sensor die bonded to the substrate at the inner region. A metal bond bonds electrodes of the sensor die to the electrical contact pads. The metal bond includes platinum, and/or one or more metals selected from tin, indium, copper, aluminum, and/or nickel.

Certain embodiments of the present disclosure relate to a sensor assembly including a housing having a first channel configured to flow a gas in a first direction and a second channel configured to flow the gas in a second direction. The housing is configured to couple to a gas flow assembly. A substrate is disposed within the housing. The substrate has an outer region, an inner region within the first channel, and a middle region between the outer region and the inner region. The substrate further includes electrical contact pads on at least the inner region. A sensor die is coupled to the inner region of the substrate, having an electrical connection to the electrical contact pads. The sensor die is disposed within a gas flow path of the first channel.

Certain embodiments of the present disclosure relate to a sensor assembly including a substrate, a housing, and a sensor die. In certain embodiments, the substrate includes an outer region, an inner region, and a middle region between the outer region and the inner region. In certain embodiments, the substrate includes electrical contact pads on at least the inner region. In certain embodiments, the housing is coupled to the substrate at the middle region or the outer region to provide a hermetic seal. In certain embodiments, the sensor die is coupled to the substrate at the inner region via the electrical contact pads. The sensor die is aligned to the substrate via aligning features that align the sensor die relative to the substrate in at least one of a first plane or a second plane.

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.