Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.

A MEMS microphone with improved sensitivity and a method for producing such a MEMS microphone are disclosed. In an embodiment the MEMS microphone includes a carrier substrate, a capacitor having two electrodes, a substrate-side anchor and an electrode anchor, wherein the substrate-side anchor connects the substrate to the capacitor, wherein the electrode anchor connects the two electrodes of the capacitor, wherein one of the electrodes is a backplate and the other electrode is the anchored membrane, and wherein the substrate-side anchor has a bearing area on the substrate which exceeds a minimum area necessary for a mechanical stability of the MEMS microphone by not more than the minimum area.

The present disclosure provides a method for processing a conductive structure. The method includes the following steps of: forming on a first surface a groove concave from the first surface towards a second surface by means of dry etching; extending the groove from the second surface to form a via through a silicon base; and processing a conductive structure within the via. The method can be applied to a silicon base having a thickness larger than 300 m. It breaks the limit on thickness that can be processed in the related art and is capable of providing electrical connectivity on both sides of a silicon base. The method is simple and highly reliable, has high processing efficiency and is applicable to mechanized production.

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

A semiconductor device includes: a silicon layer in which a trench is disposed; a surface structure portion disposed on the silicon layer at a position distant from the trench and having a surface provided by a metal layer; and a low electric conductivity portion disposed on the surface of the metal layer or in a part of the resist disposed on the trench side of the metal layer, and having an electric conductivity lower than at least a part of the metal layer covering a trench side portion of the surface of the metal layer.

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

Techniques regarding a vertical nanofluidic channel array are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a semiconductor substrate and a dielectric layer adjacent to the semiconductor substrate. The dielectric layer can comprise a first nanofluidic channel and a second nanofluidic channel. The second nanofluidic channel can be located between the first nanofluidic channel and the semiconductor substrate.

A method for fabricating a symmetrical MEMS accelerometer. For each half, etch multiple holes on the bottom of an SOI wafer; form multiple hollowed parts on the top of a silicon wafer; form silicon dioxide on the top and bottom of the silicon wafer; bond the top of the silicon wafer with the bottom of the SOI wafer; deposit silicon nitride on the bottom of the silicon wafer, remove parts of the silicon nitride and silicon dioxide to expose the bottom of the silicon wafer; etch the exposed bottom of the silicon wafer; reduce the thickness of the SOI wafer; remove the silicon nitride and exposed bottom. Bond the two halves along their bottom surface to form the accelerometer. Form a bottom cap including electrodes. Bond the bottom cap and the accelerometer. Deposit metal on top of the silicon wafer.

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

A sensor device and a method for manufacturing the sensor device. The sensor device is equipped with an impact element that includes an inner part of dielectric bulk material and an outer part of diamond-like coating material. The inner part is made to be lower at the edges than in the middle, and the outer part is formed of a diamond-like coating layer that covers the inner part. The DLC coated impact element is mechanically more robust than the rectangular prior art structures. Furthermore, the tapered form of the impact element improves conductivity of the DLC coating such that discharge of static buildup in the impact element is effectively enabled.