B81C1/00531

OPTICAL MEMORY DEVICES USING A SILICON WIRE GRID POLARIZER AND METHODS OF MAKING AND USING

Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.

Method for processing conductive structure

The present disclosure provides a method for processing a conductive structure. The method includes the following steps of: forming on a first surface a groove concave from the first surface towards a second surface by means of dry etching; extending the groove from the second surface to form a via through a silicon base; and processing a conductive structure within the via. The method can be applied to a silicon base having a thickness larger than 300 μm. It breaks the limit on thickness that can be processed in the related art and is capable of providing electrical connectivity on both sides of a silicon base. The method is simple and highly reliable, has high processing efficiency and is applicable to mechanized production.

Superhydrophobic and superoleophobic nanosurfaces

Devices, systems and techniques are described for producing and implementing articles and materials having nanoscale and microscale structures that exhibit superhydrophobic, superoleophobic or omniphobic surface properties and other enhanced properties. In one aspect, a surface nanostructure can be formed by adding a silicon-containing buffer layer such as silicon, silicon oxide or silicon nitride layer, followed by metal film deposition and heating to convert the metal film into balled-up, discrete islands to form an etch mask. The buffer layer can be etched using the etch mask to create an array of pillar structures underneath the etch mask, in which the pillar structures have a shape that includes cylinders, negatively tapered rods, or cones and are vertically aligned. In another aspect, a method of fabricating microscale or nanoscale polymer or metal structures on a substrate is made by photolithography and/or nano imprinting lithography.

Ultrasonic transducer and method for manufacturing the same, display substrate and method for manufacturing the same
11088314 · 2021-08-10 · ·

The present disclosure provides an ultrasonic transducer and a method for manufacturing an ultrasonic transducer, a display substrate and a method for manufacturing a display substrate. The method for manufacturing the ultrasonic transducer includes: forming a via hole in a substrate; forming a structural layer on a side of the substrate, the structural layer cover the via hole; and etching the structural layer from a side of the substrate away from the structural layer by using the substrate formed with the via hole as a blocking layer, to form a cavity at a position of the structural layer corresponding to that of the via hole.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

A method of manufacturing a semiconductor device includes providing a semiconductor layer having a first-type region and a second-type region that are stacked and interface with each other to form a p-n junction, the first-type region defining a first side of the semiconductor layer and the second-type region defining a second side of the semiconductor layer. The method further includes providing an insulating layer on the second side of the semiconductor layer and etching the semiconductor layer from the first side of the semiconductor layer toward the second side of the semiconductor layer to form a trench. The first-type region corresponds to one of a n-type region and a p-type region, and the second-type region corresponds to the other of the n-type region and the p-type region.

Segmented pedestal for mounting device on chip

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

MANUFACTURING METHOD OF MICRO FLUID ACTUATOR

A manufacturing method of micro fluid actuator includes: providing a substrate; depositing a first protection layer on a first surface of the substrate; depositing an actuation region on the first protection layer; applying lithography dry etching to a portion of the first protection layer to produce at least one first protection layer flow channel; applying wet etching to a portion of a main structure of the substrate to produce a chamber body and a first polycrystalline silicon flow channel region, while a region of an oxidation layer middle section of the main structure is not etched; applying reactive-ion etching to a portion of a second surface of the substrate to produce at least one substrate silicon flow channel; and applying dry etching to a portion of a silicon dioxide layer to produce at least one silicon dioxide flow channel.

ENHANCED CONTROL OF SHUTTLE MASS MOTION IN MEMS DEVICES

A MEMS device and a method of forming the same. A disclosed method includes: providing a silicon substrate layer, a buried oxide layer and a device silicon layer; using a microfabrication process to pattern a set of device features on the device silicon layer including a shuttle mass and an anchor frame; removing the silicon substrate layer and buried oxide below the shuttle mass; placing a shadow mask on a surface of the device silicon layer, wherein the shadow mask has a microscale opening to expose at least one device feature; and forming a nanoscale stopper on a sidewall of the at least one device feature by depositing a deposition material through the opening in a controlled manner.

Optical memory devices using a silicon wire grid polarizer and methods of making and using

Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.

Methods for multiple-patterning nanosphere lithography for fabrication of periodic three-dimensional hierarchical nanostructures

A robust and general fabrication/manufacturing method is described herein for the fabrication of periodic three-dimensional (3D) hierarchical nanostructures in a highly scalable and tunable manner. This nanofabrication technique exploits the selected and repeated etching of spherical particles that serve as resist material and that can be shaped in parallel for each processing step. The method enables the fabrication of periodic, vertically aligned nanotubes at the wafer scale with nanometer-scale control in three dimensions including outer/inner diameters, heights/hole-depths, and pitches. The method was utilized to construct 3D periodic hierarchical hybrid silicon and hybrid nanostructures such as multi-level solid/hollow nanotowers where the height and diameter of each level of each structure can be configured precisely as well as 3D concentric plasmonic supported metal nanodisk/nanorings with tunable optical properties on a variety of substrates.