Patent classifications
B81C1/00539
PRODUCTION METHOD FOR FABRY-PEROT INTERFERENCE FILTER
A method of manufacturing a Fabry-Perot interference filter includes a forming step of forming a first thinned region, a first mirror layer, a sacrificial layer, and a second mirror layer are formed on a first main surface of a wafer, and the first thinned region in which at least one of the first mirror layer, the sacrificial layer, and the second mirror layer is partially thinned along each of a plurality of lines is formed; a cutting step of cutting the wafer into a plurality of substrates along each of the plurality of lines by forming a modified region within the wafer along each of the plurality of lines through irradiation of a laser light, after the forming step; and a removing step of removing a portion from the sacrificial layer through etching, between the forming step and the cutting step or after the cutting step.
Nanopatterned biosensor electrode for enhanced sensor signal and sensitivity
Methods for forming an electrode structure, which can be used as a biosensor, are provided in which the electrode structure has non-random topography located on one surface of an electrode base. In some embodiments, an electrode structure is obtained that contains no interface between the non-random topography of the electrode structure and the electrode base of the electrode structure. In other embodiments, electrode structures are obtained that have an interface between the non-random topography of the electrode structure and the electrode base of the electrode structure.
RELEASE CHEMICAL PROTECTION FOR INTEGRATED COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) AND MICRO-ELECTRO-MECHANICAL (MEMS) DEVICES
Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
Aqueous formulations for removing metal hard mask and post-etch residue with Cu/W compatibility
Compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to metal conducting, e.g., tungsten, and insulating materials from a microelectronic device having same thereon. The removal compositions are low pH and contain at least one oxidizing agent and at least one etchant as well as corrosion inhibitors to minimize metal erosion and passivating agents to protect dielectric materials.
Spectrally and temporally engineered processing using photoelectrochemistry
Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.
METHOD FOR PROTECTING A MEMS UNIT AGAINST INFRARED INVESTIGATIONS AND MEMS UNIT
A method is provided for protecting a MEMS unit, in particular a MEMS sensor, against infrared investigations, a surface patterning being performed for at least one first area of a surface of the MEMS unit, the first area absorbing, reflecting or diffusely scattering more than 50%, in particular more than 90% of an infrared light incident upon it.
Spectrally and Temporally Engineered Processing using Photoelectrochemistry
Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.
Island etched filter passages
A method comprises forming etching islands on a substrate and exposing the substrate with etching islands to a solution that reacts with the etching islands to form a filter passage of interconnected pores in the substrate. The filter passage has an inlet into the substrate and an outlet from the substrate.
Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices
Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.
NANOPATTERNED BIOSENSOR ELECTRODE FOR ENHANCED SENSOR SIGNAL AND SENSITIVITY
Methods for forming an electrode structure, which can be used as a biosensor, are provided in which the electrode structure has non-random topography located on one surface of an electrode base. In some embodiments, an electrode structure is obtained that contains no interface between the non-random topography of the electrode structure and the electrode base of the electrode structure. In other embodiments, electrode structures are obtained that have an interface between the non-random topography of the electrode structure and the electrode base of the electrode structure.