B81C1/00539

Method for producing a microstructure component, microstructure component and x-ray device
10714228 · 2020-07-14 · ·

A method for producing a microstructure component, a microstructure component and an x-ray device are disclosed. In the method, a plurality of punctiform injection structures are inserted in a grid in a first substrate direction and a second substrate direction, standing at right angles thereto, into a first surface of a wafer-like silicon substrate. The injection structures are lengthened into drilled holes in the depth direction of the silicon substrate in a first etching step. A second surface of the silicon substrate is then at least partly removed for rear-side opening of the drilled holes in a second etching step and in a third etching step, an etching medium acting anisotropically is poured alternately through the drilled holes from both surfaces of the silicon substrate, so that drilled holes arranged next to one another in the first substrate direction connect to form a column running in the first substrate direction.

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) MICRO ELECTRO-MECHANICAL (MEMS) MICROPHONE AND METHOD FOR FABRICATING THE SAME
20200207613 · 2020-07-02 ·

A complementary metal-oxide-semiconductor (CMOS) micro electro-mechanical system (MEMS) microphone and a method for fabricating the same are disclosed. Firstly, a CMOS device including a semiconductor substrate, a first oxide insulation layer, a doped polysilicon layer, a second oxide insulation layer, a patterned polysilicon layer, and a metal wiring layer from bottom to top. The metal wiring layer is formed on the second oxide insulation layer. The patterned polysilicon layer includes undoped polysilicon. Then, a part of the metal wiring layer is removed to form a metal electrode and the semiconductor substrate is penetrated to have a chamber and expose the first oxide insulation layer, thereby forming a MEMS microphone.

SINGLE CRYSTALLINE DIAMOND PART PRODUCTION METHOD FOR STAND ALONE SINGLE CRYSTALLINE MECHANICAL AND OPTICAL COMPONENT PRODUCTION

The present invention relates to a free-standing single crystalline diamond part and a single crystalline diamond part production method. The method includes the steps of: providing a single crystalline diamond substrate or layer; providing a first adhesion layer on the substrate or layer; providing a second adhesion layer on the first adhesion layer: providing a mask layer on the second adhesion layer; forming at least one indentation or a plurality of indentations through the mask layer and the first and second adhesion layers to expose a portion or portions of the single crystalline diamond substrate or layer; and etching the exposed portion or portions of the single crystalline diamond substrate or layer and etching entirely through the single crystalline diamond substrate or layer.

Vertically stacked nanofluidic channel array

Techniques regarding a vertical nanofluidic channel array are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a semiconductor substrate and a dielectric layer adjacent to the semiconductor substrate. The dielectric layer can comprise a first nanofluidic channel and a second nanofluidic channel. The second nanofluidic channel can be located between the first nanofluidic channel and the semiconductor substrate.

METHOD FOR FABRICATING MICROFLUIDIC DEVICES IN FUSED SILICA BY PICOSECOND LASER IRRADIATION
20200189028 · 2020-06-18 ·

Method of fabricating a microfluidic device by means of inducing internal cracks in fused silica employing a picosecond laser beam, firstly utilizing irradiation of a focused temporally controlled picosecond laser beam in fused silica to generate a spatially selective modification region including randomly oriented nanocracks, then employing chemical etching to remove the irradiated area and obtain a hollow and connected three-dimensional microstructure, thereby achieving three-dimensional fabrication of microchannel structures inside the fused silica. The method can realize polarization insensitive three-dimensional uniform etching by regulating the pulse width of the picosecond laser beam, and has high chemical etch rate and selectivity, applicable for fabrication of large-sized three-dimensional microfluidic systems, high-precision 3D glass printing, etc.

Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

Fabrication process for a symmetrical MEMS accelerometer

A process for fabricating a symmetrical MEMS accelerometer. A pair of half parts is fabricated by, for each half part: (i) forming a plurality of resilient beams, first connecting parts, second connecting parts, and a plurality of comb structures, by etching a plurality of holes on a bottom surface of a first silicon wafer; (ii) etching a plurality of hollowed parts on a top surface of a second silicon wafer; (iii) forming a silicon dioxide layer on the top and bottom surface of the second silicon wafer; (iv) bonding the bottom surface of the first silicon wafer with the top surface of the second silicon wafer; (v) depositing a layer of silicon nitride on the bottom surface of the second silicon wafer, and removing parts of the silicon nitride layer and silicon dioxide layer on the bottom surface of the second silicon wafer; (vii) deep etching the exposed parts of the bottom surface of the second silicon wafer to the silicon dioxide layer located on the top surface of the second silicon wafer, and reducing the thickness of the first silicon wafer; and (viii) removing the silicon nitride layer, and etching the silicon dioxide to form the mass. The two half parts are then bonded along their bottom surface. The device is deep etched to form a movable accelerometer. A bottom cap is fabricated by hollowing out the corresponding area, and depositing metal as electrodes. The accelerometer is bonded with the bottom cap. Metal is deposited on the first silicon wafer to form electrodes.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Described herein is a technique capable of forming a sacrificial film with a high wet etching rate to obtain a wet etching selectivity with respect to a movable electrode when manufacturing a cantilever structure sensor using MEMS (Micro-Electro-Mechanical Systems) technology. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) loading a substrate including a control electrode, a pedestal and a counter electrode formed thereon into a process chamber; and (b) forming a sacrificial film containing impurities on the control electrode, the pedestal and the counter electrode by supplying a first process gas in a non-plasma state containing the impurities and silicon to the process chamber through a first gas supply pipe together with supplying a second process gas in a plasma state containing oxygen to the process chamber through a second gas supply pipe.

ETCHING COMPOSITION, A METHOD OF ETCHING A METAL BARRIER LAYER AND A METAL LAYER USING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

Disclosed is a method of etching a metal barrier layer and a metal layer. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.

Membrane structures for microelectromechanical pixel and display devices and systems, and methods for forming membrane structures and related devices

Embodiments relate to microelectromechanical systems (MEMS) and more particularly to membrane structures comprising pixels for use in, e.g., display devices. In embodiments, a membrane structure comprises a monocrystalline silicon membrane above a cavity formed over a silicon substrate. The membrane structure can comprise a light interference structure that, depending upon a variable distance between the membrane and the substrate, transmits or reflects different wavelengths of light. Related devices, systems and methods are also disclosed.