A manufacturing method of an electronic device includes a process that forms a protective layer on at least a portion of the first base body to which a third base body is to be bonded, a process that performs first bonding of a second base body to the first base body, a process that performs a first etching of the second base body bonded by the first bonding, a process that removes the protective layer using a second etching, and a process that performs second bonding of the third base body to the first base body. In the first etching, an etching rate of the second base body is faster than those of the first base body and the protective layer, and in the second etching, an etching rate of the protective layer is faster than those of the first base body and the second base body.

A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.

Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.

A method of manufacturing a pressure sensor is provided. The method includes: providing a substrate, wherein a bottom electrode and a pressure sensing film are disposed on the substrate; forming an etch stop assembly on the pressure sensing film at a location corresponding to a pressure trench; forming a cover layer on the substrate covering the etch stop assembly and the pressure sensing film; forming a mask layer on the cover layer, wherein an opening of the mask layer is formed above the etch stop assembly and exposes a portion of the cover layer at the location corresponding to the pressure trench; etching the cover layer using the mask layer so as to form the pressure trench in the cover layer; removing the etch stop assembly at a bottom of the pressure trench; and removing the mask layer.

A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

A Micro-Electro-Mechanical Systems (MEMS) device includes a substrate, an electronic circuit on the substrate, an electrode electrically connected to the electronic circuit, a movable element that is controlled by applying a voltage between the electrode and the movable element, an insulating layer between the electrode and the electronic circuit, and an etch stop layer. The insulating layer has a via electrically connecting the electrode and the electronic circuit, and the etch stop layer is made of at least one of Aluminum nitride or Aluminum oxide. The etch stop layer may cover the electrode and the electronic circuit, or the electrode may be mounted on the etch stop layer, electrically connected to the electronic circuit through the etch stop layer by the via.

Provided is a gas sensor including a substrate, a first membrane disposed on the substrate, a heating structure disposed on the first membrane, a second membrane disposed on the heating structure, a sensing electrode disposed on the second membrane, and a sensing material structure disposed on the sensing electrode. Here, the substrate provides an isolation space defined by a recessed surface obtained as a portion of a top surface of the substrate is spaced downward from a bottom surface of the first membrane, and the first membrane provides a first membrane etching hole that vertically extends to connect a top surface and the bottom surface of the first membrane and is connected with the isolation space. Also, the first membrane etching hole has a diameter of about 3 m to about 20 m.

A method of producing a semiconductor component having at least one exposed membrane section. A semiconductor material is provided having a carrier substrate provided with a passivation layer, where there is a membrane ply which is disposed atop the passivation layer and includes a material which is variable by water, in particular hydrolyzable, where the membrane ply is covered by a protective layer on an opposite side from the passivation layer. A portion of the carrier substrate is removed using a wet-chemical method in order to obtain an exposed region of the passivation layer in a structured region of the semiconductor material. A section of the membrane ply is exposed in the structured region by means of a first dry etching step for etching of the passivation layer and a second dry etching step for etching of the protective layer, in order to obtain the exposed membrane section.