A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

A micromechanical component for a sensor device or microphone device. The micromechanical component includes a diaphragm with a diaphragm inner side to which an electrode structure is directly or indirectly connected; and a cavity that is formed at least in a volume that is exposed by at least one removed area of at least one sacrificial layer. At least one residual area made of at least one electrically insulating sacrificial layer material of the at least one sacrificial layer is also present at the micromechanical component, and including at least one insulation area made of at least one electrically insulating material that is not the same as the electrically insulating sacrificial layer material. The electrode structure is electrically insulated from the diaphragm, and/or the at least one residual area of the at least one sacrificial layer is delimited from the cavity, using the at least one insulation area.

A micromechanical component. The micromechanical component includes: a substrate; at least one first oxide layer arranged on the substrate; and an etch stop layer arranged directly on the at least one first oxide layer; wherein a further wiring level is arranged on a bottom side of the etch stop layer.

Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective layer covering the semiconductor substrate; and removing at least one layer of the multilayer film to form a cavity that is defined by the capping layer and a remaining multilayer film that has the at least one layer removed. The thus formed semiconductor device does not have cracks in the steps of the capping layer when performing an etch process, thereby improving the performance of the semiconductor device.

The present invention generally relates to a method for forming a MEMS device and a MEMS device formed by the method. When forming the MEMS device, sacrificial material is deposited around the switching element within the cavity body. The sacrificial material is eventually removed to free the switching element in the cavity. The switching element has a thin dielectric layer thereover to prevent etchant interaction with the conductive material of the switching element. During fabrication, the dielectric layer is deposited over the sacrificial material. To ensure good adhesion between the dielectric layer and the sacrificial material, a silicon rich silicon oxide layer is deposited onto the sacrificial material before depositing the dielectric layer thereon.

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

A micro electromechanical system (MEMS) includes a substrate and a rear surface opposite to the surface, a semiconductor device and a protection wall. The substrate has a surface. The semiconductor device is disposed on the surface. The protection wall surrounds the semiconductor device and passes through the surface but not electrically contacts to the semiconductor device; wherein there is no electronic element disposed between the surface and the rear surface.

An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The second substrate is bonded to the first die so as to form a cavity, wherein a lower surface of the cavity is lined by the plasma-reflecting layer. A dielectric protection layer is present on a lower surface of the second die and lines the upper surface of the cavity. A material of the second substrate has a first etch rate for the plasma and a material of the dielectric protection layer has a second etch rate for the plasma. The second etch rate is less than the first etch rate.