A MEMS device formed in a first semiconductor substrate is sealed using a second semiconductor substrate. To achieve this, an Aluminum Germanium structure is formed above the first substrate, and a polysilicon layer is formed above the second substrate. The first substrate is covered with the second substrate so as to cause the polysilicon layer to contact the Aluminum Germanium structure. Thereafter, eutectic bonding is performed between the first and second substrates so as to cause the Aluminum Germanium structure to melt and form an AlGeSi sealant thereby to seal the MEMS device. Optionally, the Germanium Aluminum structure includes, in part, a layer of Germanium overlaying a layer of Aluminum.

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH.sub.2 species. This may be accomplished by exposing the bonding layer to an NH.sub.4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

A method of making a MEMS device including forming a mirror stack on a handle layer, applying a first bonding layer to the mirror stack, and disposing a substrate on the first bonding layer. The handle layer is removed and a second bonding layer is applied. A cap layer is disposed on the second bonding layer. The mirror stack is formed by disposing a silicon layer on the handle layer, disposing a first insulating layer on the silicon layer, etching portions of the first insulating layer, and depositing a first conductive layer on the first insulating layer. The formation also includes depositing a second insulating layer on the first conductive layer, a portion of the second insulating layer to expose a portion of the first conductive layer exposed, and forming a conductive pad on the exposed portion of the first conductive layer.

A multilayer stack comprises a surface wherein a predetermined region is defined for enclosing a device provided on the multilayer stack, the region being encircled by a welding zone defined on the surface, the welding zone being suitable for being welded by a welding radiation beam to a capping structure. It also comprises a first layer embedded within the multilayer stack, including at least one embedded component suitable for being functionally connected to the device provided on the multilayer stack. It furthermore comprises at least a second layer over the first layer comprising a shielding structure positioned between the at least one component of the first layer and the welding zone defined on the surface, the shielding structure being adapted to limit the welding depth of the welding radiation beam provided on the welding zone.

A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

The present disclosure relates to hermetic sealing of a device within a package or assembly. The sealable device is preferably a MEMS device. Surrounding the device is a first seal member that defines an internal cavity. The device can be positioned within the internal cavity, the extents of which defines a first seal region. A second seal member, and possibly others, is preferably positioned outside of the first seal member. The second seal member surrounds the first seal member a spaced distance from the first seal member to define a second seal region. Getter material is preferably placed within the first and second seal regions, and the first and second seal regions are sealed under vacuum pressure to provide a MEMS packaged assembly having a relatively low leak rate.

A method of manufacturing a dielectric barrier discharge (DBD) structure includes forming a patterned electrode layer around an outer perimeter of a substrate composed of a dielectric material. The patterned electrode layer includes multiple electrodes around the outer perimeter of the substrate and gaps between adjacent electrodes. The method further includes depositing a dielectric layer over at least a first region of the patterned electrode layer to form a DBD region of the DBD structure.

A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.

A resonance device that includes a MEMS substrate including a resonator, an upper cover, and a bonding portion that bonds the MEMS substrate to the upper cover to seal a vibration space of the resonator. The bonding portion includes a eutectic layer composed of a eutectic alloy of germanium and a metal mainly containing aluminum, a first titanium (Ti) layer, a first aluminum oxide film, and a first conductive layer consecutively arranged from the MEMS substrate to the upper cover.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.