A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

In described examples, a device mounted on a substrate includes an encapsulant. In at least one example, an encapsulant barrier is deposited along a scribe line, along which the substrate is singulatable. To encapsulate one or more terminals of the substrate, an encapsulant is deposited between the encapsulant barrier and an edge of the device parallel to the encapsulant barrier.

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a semiconductor layer, a second substrate, and a eutectic sealing structure. The semiconductor layer is over the first substrate. The semiconductor layer has a cavity at least partially through the semiconductor layer. The second substrate is over the semiconductor layer. The second substrate has a through hole. The eutectic sealing structure is on the second substrate and covers the through hole. The eutectic sealing structure comprises a first metal layer and a second metal layer eutectically bonded on the first metal layer. A method for manufacturing a semiconductor structure is also provided.

Certain embodiments of the present disclosure relate to a sensor assembly including a substrate having an outer region, an inner region, and a middle region between the outer region and the inner region. The substrate further includes electrical contact pads on at least the inner region. The sensor assembly further includes a housing coupled to the substrate at the middle region or the outer region to provide a hermetic seal. The sensor assembly further includes a sensor die bonded to the substrate at the inner region. A metal bond bonds electrodes of the sensor die to the electrical contact pads. The metal bond includes platinum, and/or one or more metals selected from tin, indium, copper, aluminum, and/or nickel.

Certain embodiments of the present disclosure relate to a sensor assembly including a housing having a first channel configured to flow a gas in a first direction and a second channel configured to flow the gas in a second direction. The housing is configured to couple to a gas flow assembly. A substrate is disposed within the housing. The substrate has an outer region, an inner region within the first channel, and a middle region between the outer region and the inner region. The substrate further includes electrical contact pads on at least the inner region. A sensor die is coupled to the inner region of the substrate, having an electrical connection to the electrical contact pads. The sensor die is disposed within a gas flow path of the first channel.

Certain embodiments of the present disclosure relate to a sensor assembly including a substrate, a housing, and a sensor die. In certain embodiments, the substrate includes an outer region, an inner region, and a middle region between the outer region and the inner region. In certain embodiments, the substrate includes electrical contact pads on at least the inner region. In certain embodiments, the housing is coupled to the substrate at the middle region or the outer region to provide a hermetic seal. In certain embodiments, the sensor die is coupled to the substrate at the inner region via the electrical contact pads. The sensor die is aligned to the substrate via aligning features that align the sensor die relative to the substrate in at least one of a first plane or a second plane.

A wireless circuit includes a housing having at least one opening, and sensor connected to the housing at the opening. The sensor includes a first layer having a first dimension and a second layer having a second dimension shorter than the first dimension. The second layer may be positioned entirely within the housing and a surface of said first layer may be exposed to an exterior of the housing.

A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.

A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.

A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.