Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

The present disclosure provides a MEMS sensor. The MEMS sensor includes a first substrate having a cavity and a second substrate bonded to the first substrate. The first substrate is provided with an electrode movably disposed in the cavity and a sealed member coupling to the second substrate. The second substrate is provided with a stop member for restricting a movement of the electrode toward the second substrate and a sealing member coupling to the sealed member. The sealed member is formed by a first metal layer on the first substrate. The sealing member is formed by a second metal layer on the second substrate. A polycrystalline layer is formed on the stop member. The polycrystalline layer is disposed between the second substrate and the second metal layer.

A method is disclosed. In one example, the method includes bonding a first panel of a first material to a base panel in a first gas atmosphere, wherein multiple hermetically sealed first cavities encapsulating gas of the first gas atmosphere are formed between the first panel and the base panel. The method further includes bonding a second panel of a second material to at least one of the base panel and the first panel, wherein multiple second cavities are formed between the second panel and the at least one of the base panel and the first panel.

A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

Some embodiments include methods of manufacturing a plurality of MEMS devices, each device including a first material and a second material with different CTE. The method includes providing a carrier with substantially equal CTE as the first material, the carrier comprising a plurality of cavities. The method also includes positioning a plurality of components in respective cavities of the carrier, the components comprising the second material. In some embodiments, the method includes positioning a layer of the first material on the second material components. In some embodiments, the method includes bonding the first material layer and the second material components. The method also includes removing the carrier and singulating the first material layer to produce the plurality of MEMS devices.

A process for manufacturing MEMS devices, includes forming a first assembly, which comprises: a dielectric region; a redistribution region; and a plurality of unit portions. Each unit portion of the first assembly includes: a die arranged in the dielectric region; and a plurality of first and second connection elements, which extend to opposite faces of the redistribution region and are connected together by paths that extend in the redistribution region, the first connection elements being coupled to the die. The process further includes: forming a second assembly which comprises a plurality of respective unit portions, each of which includes a semiconductor portion and third connection elements; mechanically coupling the first and second assemblies so as to connect the third connection elements to corresponding second connection elements; and then removing at least part of the semiconductor portion of each unit portion of the second assembly, thus forming corresponding membranes.

The present disclosure provides a CMOS structure, including a substrate, a metallization layer over the substrate, a sensing structure over the metallization layer, and a signal transmitting structure adjacent to the sensing structure. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier over the outgassing layer; and an electrode over the patterned outgassing barrier. The signal transmitting structure electrically couples the electrode and the metallization layer.

A MEMS device is disclosed. In an embodiment a MEMS device includes a substrate having an active region and at least one integrated electrical and mechanical connection element configured to electrically and mechanically mount the MEMS device to a carrier, wherein the connection element comprises a stress-reducing structure.

The present disclosure relates to semiconductor structures and, more particularly, to seal ring structures with channels and methods of manufacture. The structure includes: a first wafer having a channel formed within a passivation layer; a second wafer having a protuberance which is insertable into the channel and which is bonded to the first wafer with eutectic bonding materials; and a plurality of stoppers or tabs extending within the channel and which provides a gap that has a dimension smaller than a gap formed in other portions of the channel.

Described herein are nanopore devices as well as methods for assembling a nanopore device including one or more nanopores that can be used to detect molecules such as nucleic acids, amino acids (proteins), and the like. Specifically, a nanopore device includes an insulating layer that reduces electrical noise and thereby improves the sensing resolution of the one or more nanopores integrated within the nanopore device.