A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

A monolithic integrated device may include a first device having a complementary metal-oxide-semiconductor (CMOS) substrate, and a second device arranged over the CMOS substrate. The second device may include a first conductive element, and a second conductive element arranged over the first conductive element. A via opening may extend through the first conductive element and the second conductive element of the second device to an interconnect of the CMOS substrate. A via contact may be arranged in the via opening to contact the first conductive element, the second conductive element, and the interconnect of the CMOS substrate. The via contact electrically connects the first conductive element and the second conductive element of the second device to the interconnect of the CMOS substrate.

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.

A complementary metal oxide semiconductor (CMOS) device integrated with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device heterogeneously. For example, a CMOS wafer with CMOS devices and interconnections as well as partially processed MEMS modules is bonded with a MEMS wafer with MEMS structures, post CMOS compatibility issues are alleviated. Post integration process to complete the devices includes forming contacts for interconnecting the sensors to the CMOS components as well as encapsulating the devices with a cap wafer using wafer-level vacuum packaging.

A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.

A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

A CMOS single chip includes a movable film, at least one support pillar, a base metal layer and a circuit integration. The movable film is disposed on a top layer of the CMOS single chip and has a plurality of through-vias. The support pillar is disposed under the movable film to provide a supporting force of the movable film. The base metal layer is formed under the support pillars and isolated from the support pillars, and faces towards the movable film to form a micro capacitor to sense one of the outside sensing signals. The area of the base metal layer is larger than the area of the movable film. The circuit integration is formed under the base metal layer, or formed under the base metal layer and on the side of the movable film, and connected to the movable film and the base metal layer.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.