Patent classifications
B81C2203/0792
INTEGRATION TECHNIQUES FOR MICROMACHINED pMUT ARRAYS AND ELECTRONICS USING THERMOCOMPRESSION BONDING, EUTECTIC BONDING, AND SOLDER BONDING
The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.
Microphone package
A microphone includes a housing including a substrate and a cover disposed over the substrate, the housing including a sound port between the interior of the housing and the exterior of the housing. The microphone also includes a microelectromechanical systems (MEMS) transducer and an integrated circuit (IC) positioned within the housing and mounted on a common surface of the housing, where the MEMS transducer is electrically connected to the IC, and the IC is electrically connected to a conductor on the substrate. The microphone further includes an encapsulating material covering the IC, and an encapsulating material confinement structure disposed between the MEMS transducer and the IC, where the encapsulating material confinement structure at least partially confines the encapsulating material around the IC.
HYBRID ULTRASONIC TRANSDUCER AND METHOD OF FORMING THE SAME
A hybrid ultrasonic transducer and a method of manufacturing the same are provided. A method of manufacturing a semiconductor device includes the forming of a first substrate and a second substrate. The forming of the first substrate includes: depositing a membrane stack over a first dielectric layer; forming a third electrode over the first dielectric layer; and depositing a second dielectric layer over the membrane stack and the third electrode. The forming of the second substrate includes: forming a redistribution layer (RDL) having a fourth electrode; and etching a first cavity on a surface of the RDL adjacent to the fourth electrode. The method further includes: forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
Hybrid ultrasonic transducer and method of forming the same
A hybrid ultrasonic transducer and a method of manufacturing the same are provided. A method of manufacturing a semiconductor device includes the forming of a first substrate and a second substrate. The forming of the first substrate includes: depositing a membrane stack over a first dielectric layer; forming a third electrode over the first dielectric layer; and depositing a second dielectric layer over the membrane stack and the third electrode. The forming of the second substrate includes: forming a redistribution layer (RDL) having a fourth electrode; and etching a first cavity on a surface of the RDL adjacent to the fourth electrode. The method further includes: forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
Wafer-level fan-out package with enhanced performance
The present disclosure relates to a packaging process to enhance performance of a wafer-level package. The disclosed package includes multiple mold compounds, a multilayer redistribution structure, and a thinned die with a device layer and die bumps underneath the device layer. The multilayer redistribution structure includes package contacts at a bottom of the multilayer redistribution structure and redistribution interconnects connecting the die bumps to the package contacts. A first mold compound resides around the thinned die to encapsulate sidewalls of the thinned die, and extends beyond a top surface of the thinned die to define an opening over the thinned die. A second mold compound resides between the multilayer redistribution structure and the first mold compound to encapsulate a bottom surface of the device layer and each die bump. A third mold compound fills the opening and is in contact with the top surface of the thinned die.
MEMS STRUCTURE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a MEMS structure is provided. The method includes providing a MEMS substrate having a first surface, forming a first buffer layer on the first surface of the MEMS substrate, and forming a first roughening layer on the first buffer layer. Also, a MEMS structure is provided. The MEMS structure includes a MEMS substrate, a first buffer layer, a first roughening layer, and a CMOS substrate. The MEMS substrate has a first surface and a pillar is on the first surface. The first buffer layer is on the first surface. The first roughening layer is on the first buffer layer. The CMOS substrate has a second surface and is bonded to the MEMS substrate via the pillar. Moreover, an air gap is between the first roughening layer and the second surface of the CMOS substrate.
A SEMICONDUCTOR DEVICE HAVING MICROELECTROMECHANICAL SYSTEMS DEVICES WITH IMPROVED CAVITY PRESSURE UNIFORMITY
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.
PIEZOELECTRIC ANTI-STICTION STRUCTURE FOR MICROELECTROMECHANICAL SYSTEMS
Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure
STRUCTURE FOR MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICES TO CONTROL PRESSURE AT HIGH TEMPERATURE
Various embodiments of the present disclosure are directed towards an integrated chip including a capping structure over a device substrate. The device substrate includes a first microelectromechanical systems (MEMS) device and a second MEMS device laterally offset from the first MEMS device. The capping structure includes a first cavity overlying the first MEMS device and a second cavity overlying the second MEMS device. The first cavity has a first gas pressure and the second cavity has a second gas pressure different from the first cavity. An outgas layer abutting the first cavity. The outgas layer includes an outgas material having an outgas species. The outgas material is amorphous.
MEMS PRESSURE SENSOR
The present invention provides a MEMS pressure sensor and a manufacturing method. The pressure is formed by a top cap wafer, a MEMS wafer and a bottom cap wafer. The MEMS wafer comprises a frame and a membrane, the frame defining a cavity. The membrane is suspended by the frame over the cavity. The bottom cap wafer closes the cavity. The top cap wafer has a recess defining with the membrane a capacitance gap. The top cap wafer comprises a top cap electrode located over the membrane and forming, together with the membrane, a capacitor to detect a deflection of the membrane. Electrical contacts on the top cap wafer are connected to the top cap electrode. A vent extends from outside of the sensor into the cavity or the capacitance gap. The pressure sensor can include two cavities and two capacitance gaps to form a differential pressure sensor.