Provided is a microchip that can achieve a favorable bonding state in the bonding portion between first and second substrates even if the microchip is large in size.

A microchip includes a first substrate made of a resin and a second substrate made of a resin, the first substrate and the second substrates being bonded to each other, and a channel surrounded by a bonding portion between the first substrate and the second substrate is formed by a channel forming step formed at least in the first substrate. Further, a noncontact portion is formed to surround the bonding portion, and an angle 01 formed between a side wall surface of the channel forming step and a bonding surface continuous therewith satisfies .sub.1>90.

A DNA sequencing device and related methods, wherein the device includes a substrate, a nanochannel formed in the substrate, a first electrode positioned on a first side of the nanochannel, and a second electrode. The second electrode is positioned on a second side of the nanochannel opposite the first electrode, and is spaced apart from the first electrode to form an electrode gap that is exposed in the nanochannel. At least a portion of first electrode is movable relative to the second electrode to decrease a size of the electrode gap.

The invention relates to a method of fabricating a micro machined channel, comprising the steps of providing a substrate of a first material and having a buried layer of a different material therein, and forming at least two trenches in said substrate by removing at least part of said substrate. Said trenches are provided at a distance from each other and at least partly extend substantially parallel to each other, as well as towards said buried layer. The method comprises the step of forming at least two filled trenches by providing a second material different from said first material and filling said at least two trenches with at least said second material; forming an elongated cavity in between said filled trenches by removing at least part of said substrate extending between said filled trenches; and forming an enclosed channel by providing a layer of material in said cavity and enclosing said cavity.

In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.

Apparatus and methods for controlling the insertion of a membrane channel into a membrane are disclosed. In one arrangement a first bath holds a first liquid in contact with a first surface of a membrane. A second bath holds a second liquid in contact with a second surface of the membrane. The membrane separates the first and second liquids. A first electrode contacts the first liquid. A second electrode contacts the second liquid. A driving unit applies a potential difference across the membrane via the first and second electrodes to promote insertion of a membrane channel into the membrane from the first liquid or the second liquid. A membrane voltage reduction unit is connected in series with the membrane. The driving unit applies a driving voltage across the membrane voltage reduction unit and the membrane, the driving voltage providing the potential difference across the membrane. The membrane voltage reduction unit is configured such that a reduction in resistance through the membrane caused by insertion of a membrane channel intrinsically increases a potential difference across the membrane voltage reduction unit thereby lowering the potential difference across the membrane. The lowering of the potential difference across the membrane is sufficient to prevent or reduce promotion of insertion of a further membrane channel.

A method for fabricating calcite channels in a nanofluidic device is described. A porous membrane is attached to a substrate. Calcite is deposited in porous openings in the porous membrane attached to the substrate. A width of openings in the deposited calcite is in a range from 50 to 100 nanometers (nm). The porous membrane is etched to remove the porous membrane from the substrate to form a fabricated calcite channel structure. Each channel has a width in the range from 50 to 100 nm.

A manufacturing method of micro channel structure is disclosed and includes steps of: providing a substrate; depositing and etching to form a first insulation layer; depositing and etching to form a supporting layer; depositing and etching to form a valve layer; depositing and etching to form a second insulation layer; depositing and etching to form a vibration layer, a lower electrode layer and a piezoelectric actuating layer; providing a photoresist layer and depositing and etching to form a plurality of bonding pads; depositing and etching to from a mask layer; etching to form a first chamber; and etching to form a second chamber.

Disclosed is method of manufacturing a microchannel chip by joining together a resin channel substrate having microchannels formed on at least one side thereof and a resin lid substrate, the method including: a step (A) wherein surface modification treatment is applied on joining surfaces of the channel substrate and the lid substrate; and a step (B) wherein, after the step (A), the joining surfaces of the channel substrate and the lid substrate are mated and the channel substrate and the lid substrate are pressurized under heating via a fluid or an elastic body having a durometer hardness of E20 or less.

A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.