A MEMS device includes: a dielectric substrate; a driving electrode, first and second reference electrodes on the dielectric substrate; a first dielectric layer covering the driving electrode; and a membrane bridge on a side of the first dielectric layer away from the dielectric substrate, where a first gap is between the first reference electrode and the driving electrode; a second gap is between the second reference electrode and the driving electrode; and a thickness of a part of the first dielectric layer at each of the first and second gaps is greater than a thickness of the driving electrode; and/or, a second dielectric layer is on a side of a bridge deck of the membrane bridge close to the dielectric substrate, and an orthographic projection of the second dielectric layer on the dielectric substrate covers at least an orthographic projection of the driving electrode on the dielectric substrate.

A MEMS inertial sensor device, method of operation, and fabrication process are described wherein a MEMS inertial sensor and drive actuation units are coupled together in operational engagement, where the MEMS inertial sensor includes a substrate and a proof mass array positioned in spaced apart relationship above a surface of the substrate and constructed with a plurality of proof mass sub-structures which are each separately connected to the substrate with orthogonally disposed pairs of spring suspension structures and which are each rigidly connected to one or more adjacent proof mass sub-structures with one or more connector bars so that the plurality of proof mass sub-structures move as a single proof mass array that can operate at resonant frequencies of at least 100 kHz when oscillating in first and second orthogonal directions.

The present invention provides a new architecture of system-on-chip ultrasonic transducer array. It is based on fusion bond of two active wafers which have prefabricated CMOS integrated circuits and CMUT structures; precise thin-down of one wafer to form CMUT monocrystalline silicon membrane; and then to vertically connect CMUT array to CMOS IC layers underneath. This architecture can realize a high-density CMUT array with multiple layers of CMOS devices, such as all supporting CMOS ICs, to achieve a SOC solution. The present invention further provides a manufacturing method for above-mentioned SOC CMUT approach, and this manufacturing process can be realized in both 8 inch and 12-inch wafer manufacturing fabs. The disclosed manufacturing processes are more compatible with existing CMOS process flow, more cost-competitive for mass production.

A semiconductor device is disclosed having one or more anchors that is configured to support a moving mass. The one or more anchors are formed in or on the semiconductor substrate. The one or more anchors are attached to the semiconductor substrate. An intermediate layer is formed overlying the semiconductor substrate. A device layer is formed overlying the intermediate layer. The device layer, the intermediate layer, and the semiconductor substrate are single crystal. The moving mass is formed in the device layer. The at least one anchor comprises a dielectric material coupled to the semiconductor substrate. The moving mass couples to the at least one anchor. Portions of the intermediate layer are removed to free the moving mass in relation the semiconductor substrate.

A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a photoimageable thermoplastic polymer onto the frontside surface and into each hole; (ii) reflowing the polymer; (iii) selectively removing the polymer from regions outside a periphery of each hole, the selective removing comprising exposure and development of the polymer; (iv) optionally repeating steps (i) to (iii) until each hole is overfilled with the polymer; and (v) planarizing the frontside surface to provide one or more holes filled with a plug of the polymer. Each plug has a respective upper surface coplanar with the frontside surface.

A technique relates to a nanogap array. A substrate has been anisotropically etched with trenches that have tapered sidewalls. A sacrificial layer is on bottoms and the tapered sidewalls of the trenches. A filling material is formed on top of the sacrificial layer in the trenches. Nanogaps are formed where at least a portion of the sacrificial layer has been removed from the tapered sidewalls of the trenches while the sacrificial layer remains on the bottoms of the trenches. Each of the nanogaps is formed between one tapered sidewall of the substrate and a corresponding tapered sidewall of the filling material. The one tapered sidewall of the substrate opposes the corresponding tapered sidewall. A capping layer is disposed on top of the substrate and the filling material, such that the nanogaps are covered but not filled in.

A method for fabrication of diffractive optics by batch processing is disclosed, having applicability to high resolution ultra-high aspect ratio Fresnel Zone Plates for focusing of X-rays or gamma-rays having energies up to hundreds of keV. An array of precursor forms is etched into a planar substrate. Sidewalls of the forms are smoothed to a required surface roughness. A sequence of alternating layers of different complex refractive index, for binary or higher order diffractive optics, are deposited on the precursor forms by atomic layer deposition (ALD), to provide diffractive line patterns. Thinnest layers may have nanometer thicknesses. After front surface planarization and thinning of the substrate to expose first and second surfaces of the diffractive line patterns of the diffractive optic, the height h in the propagation direction provides a designed absorption difference and/or phase shift difference between adjacent diffractive lines. Optionally, post-processing enhances mechanical, thermal, electrical and optical properties.

Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.