Patent classifications
B81C2201/0157
METHOD TO CREATE MULTILAYER MICROFLUIDIC CHIPS USING SPIN-ON CARBON AS GAP FILL AND SPIN-ON GLASS TONE INVERSION
A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.
METHODS AND APPARATUS TO CONTROL GRAYSCALE PHOTOLITHOGRAPHY
A die includes a resist layer located over a semiconductor substrate, and a pattern developed in the resist layer. The pattern includes a plurality of locations of developed photoresist, each location of developed photoresist separated from a neighboring location of developed photoresist by a portion of undeveloped photoresist, and the developed photoresist at each location having a corresponding different thickness.
LOCALIZED FUNCTIONALIZATION OF NANOTEXTURED SURFACES
A material with a nanotexture comprising structures extending from a substrate. The structures are modified by coating the nanotexture with a protective coating and partially removing the coating, exposing a portion of the structure for functionalization.
Gradient structures interfacing microfluidics and nanofluidics, methods for fabrication and uses thereof
A fluidic chip includes at least one nanochannel array, the nanochannel array including a surface having a nanofluidic area formed in the material of the surface; a microfluidic area on said surface; a gradient interface area having a gradual elevation of height linking the microfluidic area and the nanofluidic area; and a sample reservoir capable of receiving a fluid in fluid communication with the microfluidic area. In another embodiment, a fluidic chip includes at least one nanochannel array, the nanochannel array includes a surface having a nanofluidic area formed in the material of the surface; a microfluidic area on said surface; and a gradient interface area linking the microfluidic area and the nanofluidic area, where the gradient interface area comprises a plurality of gradient structures, and the lateral spacing distance between said gradient structures decreases towards said nanofluidic area; and a sample reservoir capable of receiving a fluid in fluid communication with the microfluidic area.
Isolated protrusion/recession features in microelectromechanical systems
In described examples, a microelectromechanical system (MEMS) includes a first element and a second element. The first element is mounted on a substrate and has a first contact surface. The second element is mounted on the substrate and has a second contact surface that protrudes from the second element to form an acute contact surface. The first element and/or the second element is/are operable to move in: a first direction, such that the first contact surface comes in contact with the second contact surface; and a second direction, such that the second contact surface separates from the first contact surface.
Methods and apparatus to control grayscale photolithography
Methods and apparatus to control grayscale lithography are disclosed. A disclosed example apparatus for adjusting a grayscale lithography process includes an optical measurement device to optically measure portions of a patterned wafer, and a processor to calculate a profile based on the measured portions, and to determine an adjustment of the grayscale lithography process based on the calculated profile. The disclosed apparatus also includes an adjuster to control the grayscale lithography process based on the adjustment.
METHOD FOR ETCHING SHAPES INTO SILICON
The method described here uses gray scale lithography to form curve surfaces in photoresist. These surfaces can be of arbitrary shape since the remaining resist following exposure and develop is dependent on the exposure dose, which is controlled precisely by the opacity of the photo-mask. The process may include a silicon etch step, followed by a photoresist etch step to form an etching cycle. Each etch cycle may form a pair of substantially orthogonal stepped surfaces, with a characteristic rise and run.
PULSE TRAIN EXCITATION FOR CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER
Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.
METHOD FOR MAKING THREE DIMENSIONAL STRUCTURES USING PHOTOLITHOGRAPHY AND AN ADHESIVELY BONDABLE MATERIAL
A method for making three dimensional structures using photolithography and an adhesively bondable material is disclosed. A thiol-ene-epoxy (OSTE()) material undergoes a first reaction upon partial irradiation in a pattern to become a partially cross-linked polymer network. Non-cross-linked parts are dissolved in a solvent and removed. An initiator is added to activate the cross-linked polymer network so that it becomes adhesive and can then be covalently bound to another object to form an article. The method can be utilized to manufacture an article with a complicated three dimensional shape in an easy way.
PACKAGE SUBSTRATE INTEGRATED DEVICES
A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.