Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Methods and systems for providing a reliable (i.e., defect mitigated) isolation stack in capacitive micromachined ultrasonic transducers (CMUTs) are disclosed. A capacitive micromachined ultrasonic transducer (CMUT) includes a top electrode and a bottom electrode. The CMUT includes a sidewall between the top electrode and the bottom electrode. The sidewall is configured to separate the top electrode and the bottom electrode by a gap. The CMUT includes an isolation stack part on one or both of a bottom side of the top electrode or a top side of the bottom electrode. The isolation stack part includes a silicon dioxide layer, and a partially oxidized silicon nitride comprising a silicon nitride layer and an oxidized nitride layer.

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a MEMS device. The MEMS device includes a frame, a proof mass, and one or more curved cantilevers coupled between the frame and the proof mass. The one or more curved cantilevers have curved outer surfaces. The curved outer surfaces have a plurality of inflection points respectively arranged between turning points. The one or more curved cantilevers include four curved cantilevers respectively arranged along a different side of the proof mass.

Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

Provided is a gas sensor including a substrate, a first membrane disposed on the substrate, a heating structure disposed on the first membrane, a second membrane disposed on the heating structure, a sensing electrode disposed on the second membrane, and a sensing material structure disposed on the sensing electrode. Here, the substrate provides an isolation space defined by a recessed surface obtained as a portion of a top surface of the substrate is spaced downward from a bottom surface of the first membrane, and the first membrane provides a first membrane etching hole that vertically extends to connect a top surface and the bottom surface of the first membrane and is connected with the isolation space. Also, the first membrane etching hole has a diameter of about 3 m to about 20 m.

Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.