A complementary metal oxide semiconductor (CMOS) device integrated with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device heterogeneously. For example, a CMOS wafer with CMOS devices and interconnections as well as partially processed MEMS modules is bonded with a MEMS wafer with MEMS structures, post CMOS compatibility issues are alleviated. Post integration process to complete the devices includes forming contacts for interconnecting the sensors to the CMOS components as well as encapsulating the devices with a cap wafer using wafer-level vacuum packaging.

A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.

An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition. A second functional structure overlies the second movable membrane, where the second functional structure is laterally spaced from the first functional structure, and where the second functional structure comprises a second material having a second chemical composition different than the first chemical composition.

A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.

An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.

An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole.

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.