B01J2219/00529

METHODS AND SYSTEMS FOR MONITORING SOLID-PHASE STEPWISE OLIGONUCLEOTIDE SYNTHESIS

The present disclosure relates to method of monitoring a solid-phase reaction on a surface of a substrate by taking measurements at a plurality of positions on the surface. Properties of the surface are determined based on the measurements taken. Based on the properties determined, the extent of the solid-phase reaction is determined. This method can be achieved by using an ellipsometer and measuring the changes in thickness of the surface before and after the solid-phase reaction.

CATALYST-FREE SURFACE FUNCTIONALIZATION AND POLYMER GRAFTING
20250171604 · 2025-05-29 ·

Some embodiments described herein relate to a substrate with a surface comprising a silane or a silane derivative covalently attached to optionally substituted cycloalkene or optionally substituted heterocycloalkene for direct conjugation with a functionalized molecule of interest, such as a polymer, a hydrogel, an amino acid, a nucleoside, a nucleotide, a peptide, a polynucleotide, or a protein. In some embodiments, the silane or silane derivative contains optionally substituted norbornene or norbornene derivatives. Method for preparing a functionalized surface and the use in DNA sequencing and other diagnostic applications are also disclosed.

Increasing Efficiency Of Photochemical Reactions On Substrates
20250205671 · 2025-06-26 ·

Disclosed herein is a substrate which includes a functional group protected with a photolabile group covalently attached to the substrate and a film of solvent thereof covering the substrate, where the thickness of the film is less than about 100 m. Also disclosed herein are methods of preparing such substrates. Further disclosed are methods of synthesizing polymers, methods of synthesizing arrays of polymers and methods of removing photolabile protecting groups. These methods all employ covering the substrate with a thin film of solvent where the thickness of the film is less than 100 m.

Gene sequencing chip and gene sequencing method

A gene sequencing chip is provided, which includes: an upper substrate including a plurality of liquid inlets for inletting liquid drops; a lower substrate opposite to the upper substrate and spaced therefrom by a gap, the gap being provided for allowing the liquid drops to move therein, the lower substrate including a liquid drop operation region, the liquid drop operation region including a manipulation electrode array. The manipulation electrode array includes multiple first manipulation electrode array for preparing a gene library, multiple second manipulation electrode array for sequencing the gene library which is prepared, each first sub-array being adjacent to one of the multiple second manipulation electrode array. Based on the gene sequencing chip provided in this disclosure, operations to tiny liquid drops such as movement, fusion and splitting can be accurately manipulated by using digital microfluidic techniques, and all steps of the gene sequencing from library preparation to gene sequencing can be completed on one chip.

A MOLECULAR SYNTHESIS ARRAY

According to an aspect of the present inventive concept there is provided a molecular synthesis array (100, 100) comprising: a substrate (208, 208); an insulating layer (202, 202) arranged on the substrate (208, 208); a plurality of lower electrode lines (104) extending in parallel along a column direction of the 5 molecular synthesis array (100, 100), and a plurality of upper electrode lines (102) extending in parallel along a row direction of the molecular synthesis array (100, 100), wherein the upper electrode lines (102) are vertically separated from the lower electrode lines (210, 210) and extend across the lower electrode lines (104), and wherein the lower and upper electrode lines (210, 210, 204, 0 204) are embedded in the insulating layer (202, 202); and a plurality of synthesis wells (106), wherein each well (200, 200) is formed at a crossing between a lower electrode line (210, 210) and an upper electrode line (204, 204) and extends from an upper surface (226) of the insulating layer (202, 202) to the lower electrode line (210, 210), through the insulating layer (202, 202) 5 and through the upper electrode line (204, 204), and exposes an electrode surface portion (222, 222) of the upper electrode line (204, 204) and an electrode surface portion (216, 216) of the lower electrode line (210, 210).

A MOLECULAR SYNTHESIS ARRAY
20250352971 · 2025-11-20 ·

According to an aspect of the present inventive concept there is provided a molecular synthesis array comprising: a substrate; an insulating layer (202) arranged on the substrate; a plurality of column lines (102) extending in parallel along a column direction of the molecular synthesis array (100), and a plurality of row lines (104) extending in parallel along a row direction of the molecular synthesis array (100), wherein the column lines (102) are vertically separated from the row lines (104) and extend transverse to the row lines (104); a plurality of synthesis cells (105), wherein each cell (200) is coupled to a respective pair of a column line and a row line and comprises: a lower electrode (226) and an upper electrode (206) vertically separated from each other and embedded in the insulating layer (202), a synthesis well (223) extending from an upper surface (225) of the insulating layer (202) to the lower electrode (226), through the insulating layer (202) and through the upper electrode (206), wherein the well (223) exposes a surface portion (214) of the upper electrode (206) and a surface portion (220) of the lower electrode (226), and a select transistor (106) having a first terminal (114a), a second terminal (114b) and a gate terminal (114c), the first and second terminals (114a, 114b) forming respective source/drain terminals of the select transistor (106), wherein the gate terminal (114c) is coupled to the row line, the first terminal (114a) is coupled to the column line, the second terminal (114b) is coupled to the lower electrode (226), and the upper electrode (206) is coupled to a reference voltage, or wherein the gate terminal (114c) is coupled to the row line, the first terminal (114a) is coupled to the column line, the second terminal (114b) is coupled to the upper electrode (206), and the lower electrode (226) is coupled to a reference voltage.