A semiconductor package includes a number of different substrate sections. Each substrate section includes one or more electronic components. Additionally, each substrate section is mechanically and electrically coupled together using various conductive columns and conductive apertures. Because the substrate sections are interconnectable, a shape and/or a size of the semiconductor package is fully customizable. Additionally, a layout of the various electronic components of the semiconductor package is also fully customizable.

A chip structure including: a photonic integrated circuit (PIC) chip; an electronic integrated circuit (EIC) chip disposed on the PIC chip; and an optical block disposed on the PIC chip, spaced apart from the EIC chip in a horizontal direction, and configured to transfer optical signals to the PIC chip.

A semiconductor package may include a first redistribution structure, a sub-semiconductor package on the first redistribution structure, where the sub-semiconductor package may include a second redistribution structure, a bridge die on the second redistribution structure, a first molding material configured to cover the bridge die on the second redistribution structure, a third redistribution structure on the first molding material and on the bridge die, a first semiconductor die on the third redistribution structure, a second semiconductor die on the third redistribution structure, and beside the first semiconductor die, where the second semiconductor die is electrically connected to the first semiconductor die through the bridge die, and a second molding material configured to cover the first semiconductor die and the second semiconductor die, on the third redistribution structure, and a third molding material configured to cover the sub-semiconductor package, on the first redistribution structure.

An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

This application discloses a chip packaging structure, an electronic device, and a preparation method. The packaging structure includes: a first redistribution layer, chip wafers, a second redistribution layer, and a packaging layer. The first redistribution layer and the second redistribution layer are electrically connected to each other. The packaging layer is sandwiched between the first redistribution layer and the second redistribution layer. At least two stacked chip wafers are embedded in the packaging layer. Any two adjacent chip wafers are electrically connected to each other, and any of the chip wafers is electrically connected to at least one of the first redistribution layer and the second redistribution layer.

A semiconductor package includes a wiring structure. A buffer die is disposed on the wiring structure. A logic die is disposed alongside the buffer die on the wiring structure. A first encapsulating material covers at least a portion of each of the buffer die and the logic die. A memory stack is disposed on the buffer die and is electrically connected to the buffer die. A bridge die is disposed so as to extend over at least a portion of each of the buffer die and the logic die, and is electrically connected to each of the buffer die and the logic die. A second encapsulating material covers at least a portion of each of the memory stack and the bridge die. The buffer die and the logic die are disposed at a level that is between those of the wiring structure and the bridge die.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and a first integrated circuit chip on the interposer. The interposer includes a galvanic effect test structure including a test contact pad and a detection contact pad. The interposer includes a plurality of primary contact pads electrically coupled to the first integrated circuit chip. The galvanic effect structure can be utilized to test the interposer for galvanic corrosion prior to assembling the interposer into the integrated circuit package.

A semiconductor device with a two-sided redistribution layer is disclosed. The semiconductor device comprises a host device and one or more memory stack cubes. A redistribution layer is disposed between and couples the host device and the memory stack cubes. This redistribution layer features an edge surface extending between the host device and the memory stack cubes. The semiconductor device includes first connective circuitry that extends through the redistribution layer, is coupled with the host device, and is exposed at the edge surface of the redistribution layer. Additionally, second connective circuitry extends through the redistribution layer, is coupled with the memory stack cubes, and is exposed at the edge surface of the redistribution layer. Connective structures couple the first and second connective circuitry exposed at the edge surface of the redistribution layer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

A die substrate, including a dielectric body, the body having a first body surface, a second body surface on an opposite side and body edge surfaces located in between. Current-carrying metal lines located in the dielectric body. One or more of the metal lines routed to one or more of the body edge surfaces. A termination layer located on the at least one body edge surface and electrically connected to the least one of the metal lines routed to the body edge surfaces. Electrically conductive plating located on the at least one body edge surface. The plating connected to the termination layer for an electrical current connection or a ground connection to the at least one metal line. A method of manufacturing an integrated circuit package, the package and a computer having the die substrate are also disclosed.