Provided is a semiconductor package including a first semiconductor device, an encapsulant surrounding the first semiconductor device, an upper redistribution structure provided on the encapsulant, and a heat dissipation block provided on the upper redistribution structure. The heat dissipation block includes a first block surface facing a top surface of the upper redistribution structure, the heat dissipation block includes a first protrusion on the first block surface, a first concave portion corresponding to the first protrusion is provided on the top surface of the upper redistribution structure, the first protrusion is located in the first concave portion, and a heat transfer layer is provided between the heat dissipation block and the top surface of the upper redistribution structure.

Provided is a chip structure including a redistribution structure, an electronic integrated circuit chip on an upper surface of the redistribution structure, and a photonic integrated circuit chip including a first substrate on an upper surface of the electronic integrated circuit chip and comprising an active surface and an inactive surface opposite to the active surface, a first reflector on the inactive surface of the first substrate, and a first wiring structure on the active surface of the first substrate, the first wiring structure comprising a waveguide, a grating coupler, and a second reflector, wherein a patterned surface of the grating coupler faces the redistribution structure.

A system and a method for a semiconductor integrated package are disclosed. An interposer has a top surface and a bottom surface. A first circuit layer is disposed on the top surface by a first bonding and has at least one first circuit. A second circuit layer is disposed on the first circuit layer by a second bonding and has at least one second circuit. A thermal layer having an embedded liquid cooling channel is bonded on the second circuit layer.

The present disclosure as an embodiment is to provide a wiring structure including a first wiring pattern; an insulation layer covering at least a portion of the first wiring pattern; a second wiring pattern disposed on the insulation layer; a via penetrating at least a portion of the insulation layer and electrically connecting the first wiring pattern and the second wiring pattern; and a protruding pattern extending into the insulation layer and having at least a portion thereof embedded in the insulation layer, the protruding pattern disposed on the first wiring pattern and connected thereto, and positioned spaced apart from the via and surrounding at least a portion of the via on the first wiring pattern.

A panel-level semiconductor package structure is provided. The panel-level semiconductor package structure includes a panel-level substrate structure and at least one wafer-level package structure. The panel-level substrate structure has a first side and a second side opposite to the first side. The wafer-level package structure is bonded over the panel-level substrate structure. Each of the wafer-level package structures includes a first redistribution layer (RDL) over the elastomeric connector and a plurality of first semiconductor devices laterally disposed over the first RDL. A method for manufacturing a panel-level substrate structure is also provided.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A semiconductor package includes a redistribution layer including, a first insulating layer including a first trench, a first conductive layer including a first conductive region extending along a top surface of the first insulating layer and a second conductive region disposed inside the first trench, a second insulating layer on the first conductive layer and the first insulating layer, the second insulating layer including a second trench at least partially overlapping the first trench, the second trench exposing a part of the first conductive region and a second conductive layer including a third conductive region extending along a top surface of the second insulating layer and a fourth conductive region disposed on the second conductive region inside a via trench including sidewalls of the first trench and the second trench, and wherein the second and fourth conductive regions have a width in a range of 20 m to 600 m.

Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

The technology of this application relates to a board-level structure that includes an upper-layer substrate, a lower-layer substrate, and a plurality of support members that are supported between the upper-layer substrate and the lower-layer substrate. In an example embodiment, a gap exists between the upper-layer substrate and the lower-layer substrate, the gap includes at least one first gap region and at least one second gap region, the first gap region and the second gap region are spaced, a spaced region between the first gap region and the second gap region does not include the first gap region or the second gap region, and a maximum vertical distance between the upper-layer substrate and the lower-layer substrate in the first gap region is less than a minimum vertical distance between the upper-layer substrate and the lower-layer substrate in the second gap region.

A wiring board that facilitates narrowing a pitch of bonding terminals used for bonding to a semiconductor chip, providing finer wiring in a substrate and reducing cost, and is capable of achieving high connection reliability. A composite wiring board includes: a first wiring board; a second wiring board facing the first wiring board and bonded to the first wiring board, a distance from the second wiring board to the first wiring board being greater at a peripheral part than at a center part of the second wiring board; and a sealing resin layer interposed between the first wiring board and the second wiring board, the sealing resin layer covering an end face of the second wiring board.