A diode device includes a semiconductor substrate, isolation structures, and metal silicide layers. The semiconductor substrate includes a well region and first to third doped regions in the well region. The first and second doped regions have opposite conductivity types, and a conductivity type of the well region is the same as the conductivity type of the second doped region. The third doped region is between the first and second doped regions. A conductivity type of the third doped region is the same as the conductivity type of the first doped region, and a dopant concentration of the third doped region is greater than a dopant concentration of the first doped region. The isolation structures are in the semiconductor substrate and spacing the first to third doped regions apart from each other. The metal silicide layers are respectively over the first and second doped regions.

A semiconductor device includes a well formed in a semiconductor substrate, the well including a threshold voltage (Vt) implant. A source region and a drain region is created in the well, and a gate contact is formed over an oxide layer. The source region includes a source extension that is extended under a portion of the gate contact to create an integrated capacitor.

A trench MOSFET with reduced gate capacitances, and a method of making the same. The reduction of the gate capacitances is achieved with asymmetric dielectric gate oxide on the sidewalls and bottom of the trench, with the gate oxide being thinner on the channel side and thicker on the opposite side and bottom. Silicon is implanted into a partial MOSFET structure, resulting in silicon-rich silicon carbide. A trench is asymmetrically etched into the implanted silicon, leaving a thicker layer of the implanted silicon on the second sidewall and bottom of the trench than on the first sidewall. A layer of silicon dioxide is grown over the first and second sidewalls and bottom of the trench, and the growing oxide converts the silicon-rich silicon carbide into additional silicon dioxide, resulting in a thicker layer of silicon dioxide at the second sidewall and bottom of the trench than at the first sidewall.

Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 m or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 m or more in a direction from the local maximum of the hydrogen peak toward the upper surface.

An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

A field-effect transistor includes: a semiconductor substrate having trenches; and a gate electrode disposed in the trenches. Breakdown voltage regions are provided in each inter-trench range. The breakdown voltage regions are arranged to form rows extending in a first direction intersecting the trenches. The rows are arranged at interval in a second direction parallel to the trenches. Each of the breakdown voltage regions extends from an upper side of a lower end of each of the trenches to a lower side of the lower end of each of the trenches, and is disposed at a distance from a gate insulating film. A drift region is in contact with the gate insulating film at a position between the breakdown voltage region and the gate insulating film.

A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

A power element and a manufacturing method for the power element are provided. The power element that is manufactured is a trench-type metal oxide semiconductor field-effect transistor having a junction field-effect transistor region. The power element includes a substrate, a drift diffusion layer, a body layer, a plurality of gate trenches, polycrystalline silicon, a plurality of first doped regions, a plurality of second doped regions, a plurality of protective doped regions, a plurality of dielectric layers, and a metal conductive layer.

In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.