A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.

An integrated device package is disclosed. The integrated device package can include a carrier that has a multilayer structure having a first layer and a second layer. The first layer at least partially defines a lower side of the carrier. An electrical resistance of the second layer is greater than an electrical resistance of the first layer. The integrated device package can include a microelectronicmechanical systems die that is mounted on an upper side of the carrier opposite the lower side. The integrated device package can include a lid that is coupled to the carrier. The lid and the microelectronicmechanical systems die are spaced by a gap defining a back volume.

A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.

A semiconductor package includes a first substrate, a first semiconductor chip, a first bonding wire, a second substrate, a second semiconductor chip and a second bonding wire. The first substrate has a window through a center portion of the first substrate. The first semiconductor chip is located on the first substrate. The first bonding wire is in the window of the first substrate and electrically connects to the first semiconductor chip and the first substrate. The second substrate is located on the first semiconductor chip, and has a window through a center portion of the second substrate. The second substrate electrically connects to the first substrate. The second semiconductor chip is located on the second substrate. The second bonding wire is in the window of the second substrate and electrically connects to the second semiconductor chip and the second substrate.

A cooling device including a rectangular top plate in a plan view having a front surface on which a semiconductor module is disposed and a rear surface having a sidewall connection region, a flow pass region, and an outer edge region. The flow pass region includes a cooling region and first and second communicating regions that sandwich the cooling region therebetween from a short-side direction of the top plate. The sidewall connection region surrounds an outer periphery of the flow pass region. The outer edge region is outside of the sidewall connection region and closer to an edge of the top plate than is the flow pass region. The cooling region has a first thickness, and the outer edge region has a second thickness that is greater than the first thickness.

A semiconductor package includes a lower redistribution wiring layer; and a first semiconductor device on the lower redistribution wiring layer, the first semiconductor device being connected to the lower redistribution wiring layer via conductive bumps, wherein the lower redistribution wiring layer includes: a first redistribution wire in a first lower insulating layer; an insulating structure layer having an opening that exposes a portion of the first redistribution wire, the insulating structure layer including a first photosensitive insulating layer, a light blocking layer on the first photosensitive insulating layer, and a second photosensitive insulating layer on the light blocking layer; a second redistribution wire in the opening of the insulating structure layer, the second redistribution wire including a redistribution via contacting the first redistribution wire, and a redistribution line stacked on the redistribution via; and bonding pads bonded to the conductive bumps and electrically connected to the second redistribution wire.

A semiconductor device includes: a baseplate; an insulating substrate on the baseplate; a semiconductor element on the insulating substrate; a case bonded to the baseplate by an adhesive, the case surrounding a space in which the semiconductor element is positioned; and an encapsulating material filling the space surrounded by the case, in which, the case includes a claw, the claw includes: a protrusion protruding from an inner wall surface of the case; and a hook inclined from the protrusion, a space being sandwiched between the hook and the inner wall surface of the case.

The semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, a transistor, and a through-silicon-via (TSV) structure. The transistor is over the substrate. The TSV structure penetrates the substrate and comprises a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is between the first conductive layer and the second conductive layer. The method of manufacturing the same includes the following steps: forming a via hole in a substrate; forming a first conductive layer in the via hole; forming a dielectric layer in the via hole and over the first conductive layer; forming a second conductive layer in the via hole and over the dielectric layer; and forming a transistor over the substrate. The first conductive layer, the dielectric layer, and the second conductive layer collectively form a through-silicon-via (TSV) structure.

Various aspects of the present disclosure generally relate to an integrated circuit device, such as a packaged integrated circuit device. In some aspects, an integrated circuit device includes a semiconductor die and a lid thermally coupled to the semiconductor die. The lid includes a two-phase thermal management device. The integrated circuit device also includes an interface layer in contact with the semiconductor die and the lid.