A semiconductor package structure and a method for preparing the same are provided. The semiconductor package structure includes: a substrate; a first semiconductor chip located on the substrate, the first semiconductor chip having a first surface that is bare and the first surface having a silicon-containing surface; second semiconductor chip structures located on the first surface of the first semiconductor chip, the second semiconductor chip structures having second surfaces opposite to the first surface; a first package compound structure having a joint surface, the joint surface covering at least the first surface of the first semiconductor chip and the second surfaces of the second semiconductor chip structures. The joint surface has a silicon-containing surface.

A semiconductor package includes a first substrate, a first semiconductor chip, a first bonding wire, a second substrate, a second semiconductor chip and a second bonding wire. The first substrate has a window through a center portion of the first substrate. The first semiconductor chip is located on the first substrate. The first bonding wire is in the window of the first substrate and electrically connects to the first semiconductor chip and the first substrate. The second substrate is located on the first semiconductor chip, and has a window through a center portion of the second substrate. The second substrate electrically connects to the first substrate. The second semiconductor chip is located on the second substrate. The second bonding wire is in the window of the second substrate and electrically connects to the second semiconductor chip and the second substrate.

A semiconductor package includes a lower redistribution wiring layer; and a first semiconductor device on the lower redistribution wiring layer, the first semiconductor device being connected to the lower redistribution wiring layer via conductive bumps, wherein the lower redistribution wiring layer includes: a first redistribution wire in a first lower insulating layer; an insulating structure layer having an opening that exposes a portion of the first redistribution wire, the insulating structure layer including a first photosensitive insulating layer, a light blocking layer on the first photosensitive insulating layer, and a second photosensitive insulating layer on the light blocking layer; a second redistribution wire in the opening of the insulating structure layer, the second redistribution wire including a redistribution via contacting the first redistribution wire, and a redistribution line stacked on the redistribution via; and bonding pads bonded to the conductive bumps and electrically connected to the second redistribution wire.

A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe including a die pad, a first ridge formed at a first outer edge of the die pad, a second ridge formed at a second outer edge of the die pad opposite of the first outer edge and separate from the first ridge, and a plurality of leads surrounding the die pad. A semiconductor die is attached to the die pad by way of a die attach material. The semiconductor die is located on the die pad between the first ridge and the second ridge. An encapsulant encapsulates the semiconductor die and at least a portion of the package leadframe.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

A lead frame according to the present embodiments includes: a main body portion having a main surface including a mounting region on which a semiconductor chip is to be mounted; a lead portion connected to the main body portion; a groove portion provided in a main surface of the main body portion so as to surround the mounting region, the groove portion having an inner side surface and an outer side surface; and a protruding portion protrudingly provided along an inner edge of the groove portion.

Provided is a semiconductor package including a first semiconductor chip; a plurality of lower first conductive posts on the first semiconductor chip; a second semiconductor chip offset-stacked on the first semiconductor chip; a plurality of lower second conductive posts on the second semiconductor chip; a first molding layer around the first semiconductor chip, and the second semiconductor chip; a third adhesive layer on an upper surface of the first molding layer; a plurality of upper first conductive posts on the plurality of lower first conductive posts; a plurality of upper second conductive posts on the plurality of lower second conductive posts; a third semiconductor chip on the third adhesive layer; a plurality of third conductive posts on the third semiconductor chip; a second molding layer on the third adhesive layer; and a redistribution structure on the second molding layer.

Disclosed herein is a multi-die device, and an integrated chip package assembly having the multi-die device. The multi-die device includes a first IC die and a second IC die disposed at a same tier; a first conductive pillar coupled with the first IC die; a second conductive pillar coupled with the second IC die; and an interconnecting die disposed between the first conductive pillar and the second conductive pillar and configured to couple with the first IC die and the second IC die. The multi-die device further includes a first interconnecting interface disposed on the first IC die; a second interconnecting interface disposed on the second IC die, the first interconnecting interface and the second interconnecting interface being separated by a molding material.

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

The present invention relates to a layer formation method and, more specifically, to a semiconductor device manufacturing method for forming a semiconductor device through a low-temperature process. The layer formation method according to an embodiment of the present invention is a method for manufacturing a semiconductor device which comprises a silicon substrate containing germanium (Ge) or a substrate on which a silicon layer containing germanium (Ge) is formed, and which comprises an undoped gallium nitride (GaN) layer, an N-type gallium nitride (GaN) layer, an active layer and a P-type gallium nitride (GaN) layer, wherein a step of forming at least one gallium nitride layer from among the undoped gallium nitride (GaN) layer, the N-type gallium nitride (GaN) layer, the active layer and the P-type gallium nitride (GaN) layer comprises the steps of: a) sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor at 500 C. or lower, thereby forming a gallium nitride (GaN) layer on the substrate; and b) exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma, and steps a) and b) are repeated multiple times.