A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.

A power electronics module, having a DBC PCB having power semiconductors arranged thereon, and a multilayered leadframe including at least two separate subframes. No power or control routing takes place on the PCB. A region of the load source subregion is arranged between the PCB and the gate source and kelvin source subregion and is in electrical contact with the power semiconductors, and an adjoining region is located outside the PCB. A region of the drain source subregion is in electrical contact with a drain terminal on the PCB, and an adjoining region is located outside the PCB. The gate source subregion and the kelvin source subregion have a region above the load source subregion at which said subregions are in electrical contact with the power semiconductors and have an adjoining region outside the PCB which is opposite the drain source subregion and has pins bent above the PCB.

A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding layer has a graphene core shell formed on a surface of the encapsulant. The shielding layer can be printed on the encapsulant. The graphene core shell includes a copper core. The shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the shielding layer to form an electrical path. The shielding layer also has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the matrix. A shielding material can be disposed around the electrical component. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

A power semiconductor package includes a substrate, a power semiconductor chip arranged on the substrate, and an encapsulant encapsulating the power semiconductor chip. The encapsulant includes a voltage stabilizing additive. The voltage stabilizing additive is configured to minimize or eliminate partial discharges within the encapsulant.

A packaging structure and a formation method thereof are provided. The packaging structure includes a carrier board, and a plurality of semiconductor chips adhered to the carrier board. Each semiconductor chip has a functional surface and a non-functional surface opposite to the functional surface, and a plurality of pads are formed on the functional surface of a semiconductor chip of the plurality of chips. A metal bump is formed on a surface of a pad of the plurality of pads, and a first encapsulation layer is formed on the functional surface. The packaging structure also includes a second encapsulation layer formed over the carrier board.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

A method for making a semiconductor device is provided. The method includes: providing a package including: a substrate including a top surface and a bottom surface; a top electronic component mounted on the top surface of the substrate; at least one conductive pillar formed on the bottom surface of the substrate; and a protection layer attached on the bottom surface of the substrate and covering the at least one conductive pillar; providing a molding apparatus including a top chase and a bottom chase, wherein a molding material is held in the bottom chase; attaching the protection layer onto the top chase of the molding apparatus; and moving the top chase and the bottom chase close to each other to compress the molding material to cover the top electronic component on the top surface of the substrate, thereby forming a top encapsulation on the top surface of the substrate.