A semiconductor memory device includes a substrate, a capacitor structure including a lower electrode electrically connected to a storage pad, a capacitor dielectric film, and an upper electrode, a cell metal contact contacting an upper surface of the upper electrode, a first peripheral contact plug electrically connected to the substrate, a first peripheral wiring pad in a first interlayer insulating film on the storage pad, a second peripheral contact plug electrically connected to the first peripheral wiring pad, a second peripheral wiring pad contacting the second peripheral contact plug, and a peripheral metal contact electrically connected to the second peripheral wiring pad, wherein a vertical surface of the second peripheral wiring pad is at a level of the upper surface of the upper electrode, and a bottom surface level of the capacitor structure is at a vertical level of an upper surface of the first peripheral wiring pad.

A method of forming a memory cell and a method of forming a selector are provided. The method of forming the memory cell includes forming a selector over a substrate, including: forming a bottom electrode; forming an ovonic threshold switch layer on the bottom electrode; forming an inter-electrode over the ovonic threshold switch layer; forming an intermediate layer between the ovonic threshold switch layer and the inter-electrode; and forming a memory element on the selector; and forming a connecting pad on the memory element. The intermediate layer has a curved sidewall extending from a top surface of the ovonic threshold switch layer to a bottom surface of the inter-electrode.

A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source/drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

There is provided a semiconductor device with improved integration and performance. The semiconductor device includes a substrate, a first lower active pattern, a first upper active pattern on the first lower active pattern, a first gate structure on the first lower active pattern and the first upper active pattern, a second lower active pattern spaced apart from the first lower active pattern, a second upper active pattern on the second lower active pattern and spaced apart from the first upper active pattern, a second gate structure on the second lower active pattern and the second upper active pattern, a first source/drain contact electrically connected to a first lower source/drain region of the first lower active pattern and a first upper source/drain region of the first upper active pattern and a first back connecting wire and electrically connecting the first source/drain contact and the second gate structure.

A semiconductor device includes a substrate, a semiconductor layer, a conductor layer, and wiring. The semiconductor layer is provided on a surface side of the substrate and includes a first portion and a second portion with a larger surface area than the first portion. The conductor layer is provided on an opposite side of the second portion to the substrate. The wiring passes through the substrate and is connected to the conductor layer.

A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.

Aspects of the disclosure provide a semiconductor device and a method to fabricate the semiconductor device. The semiconductor device includes a first die comprising a first contact structure formed on a face side of the first die. The semiconductor device includes a first semiconductor structure and a first pad structure that are disposed on a back side of the first die. The first semiconductor structure is conductively connected with the first contact structure from the back side of the first die and the first pad structure is conductively coupled with the first semiconductor structure. An end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. The first die and a second die can be bonded face-to-face.