A microelectronic device may include a plane comprising blocks horizontally extending in parallel in a first direction and horizontally alternating with slot structures in a second direction orthogonal to the first direction. The blocks may include tiers individually including conductive material and insulative material vertically neighboring the conductive material. The device may also include an additional plane horizontally neighboring the plane in the second direction and including additional blocks similar to the blocks. At least one source structure may vertically underlie and horizontally overlap horizontal areas of the plane and the additional plane. A plane separation region may be interposed between the plane and the additional plane in the second direction. The plane separation region may have a horizontal width in the second direction that is less than or equal to a combined horizontal width in the second direction of one of the blocks and two of the slot structures.

An integrated circuit comprising: a plurality of devices arranged on a front side of a substrate; a first backside pattern and a second backside pattern, wherein the first backside pattern and the second backside pattern extend in a first direction along a first track in a first backside wiring layer, wherein the first backside wiring layer is on a back side of the substrate, and wherein the first backside pattern and the second backside pattern are configured to receive a first supply voltage and provide the first supply voltage to at least one of the plurality of devices; and a third backside pattern extending in the first direction along the first track between the first backside pattern and the second backside pattern, in the first backside wiring layer, wherein the third backside pattern is configured to receive a source supply voltage and provide the source supply voltage to a first device of the plurality of devices.

An apparatus, a method and a system. The apparatus comprises a memory array including word lines defining a staircase structure, and a staircase etch stop layer including: a sandwich etch stop layer disposed on a top region the staircase and including a first etch stop layer and a third etch stop layer of a first material, and a second etch stop layer sandwiched between the first etch stop layer and the third etch stop layer and made of a second material having etch properties different from the first material; a precut etch stop layer disposed at a region of the staircase structure below the top region and including the second etch stop layer and the third etch stop layer and not the first etch stop layer; and contact structures extending through a dielectric layer and the staircase etch stop layer and landing on the word lines at the staircase structure.

An electronic network device includes a package substrate, an Integrated Circuit (IC) mounted on the package substrate, and a plurality of interconnection terminals disposed on a surface of the package substrate. The interconnection terminals include multiple pairs of signal terminals and multiple ground terminals. The interconnection terminals are arranged in a hexagonal grid in which (i) a given interconnection terminal is surrounded by six other interconnection terminals, and (ii) propagation paths between signal terminals that do not belong to a same pair are at least partially blocked by the ground terminals.

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Backside contacts wrapping around source/drain regions provide increased contact areas for electrical connections between field-effect transistors and metallization layers. Cavities formed within a device layer expose sidewalls of selected source/drain regions. The backside contacts extend within such cavities and adjoin the sidewall surfaces and bottom surfaces of the selected source/drain regions.

A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.