This invention provides opportunity for diamond and bi-wafer microstructures to be implemented in advanced ICs and advanced IC packages to form a new breed of ICs and SiPs that go beyond the limitations of silicon at the forefront of IC advancement due primarily to diamond's extreme heat dissipating ability. Establishing the diamond and bi-wafer microstructure capabilities and implementing them in advanced ICs and advanced IC packages gives IC and package architects and designers an extra degree of design freedom in achieving extreme IC performance, particularly when thermal management presents a challenge. Diamond's extreme heat spreading ability can be used to dissipate hotspots in processors and other high-power chips such as GaN HEMT, resulting in performance and reliability enhancement for IC and package applications covering HPC, AI, photonics, 5G RF/mmWave, power and IoT, and at the system level propelling the migration from traditional computing to near-memory computing and in-memory computing.

A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a flex circuit coupled to the semiconductor die.

A power electronics module, having a DBC PCB having power semiconductors arranged thereon, and a multilayered leadframe including at least two separate subframes. No power or control routing takes place on the PCB. A region of the load source subregion is arranged between the PCB and the gate source and kelvin source subregion and is in electrical contact with the power semiconductors, and an adjoining region is located outside the PCB. A region of the drain source subregion is in electrical contact with a drain terminal on the PCB, and an adjoining region is located outside the PCB. The gate source subregion and the kelvin source subregion have a region above the load source subregion at which said subregions are in electrical contact with the power semiconductors and have an adjoining region outside the PCB which is opposite the drain source subregion and has pins bent above the PCB.

A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.

A power electronics module, having a PCB having power semiconductors arranged on connecting regions of an uppermost layer of said PCB, wherein the PCB has a preset dimension to arrange a preset maximum number of power semiconductors thereon. A lead frame arranged above the power semiconductors provides three-dimensional power and control routing, and includes a drain-source connection to connect to a drain-source contact of the PCB, and a load-source connection opposite the drain-source connection via the power semiconductors that is formed from a plurality of subregions, each of which can be brought into electrical contact with the power semiconductors, and a gate- and kelvin-source terminal, which are arranged above the load-source connection and have been brought into electrical contact with the power semiconductors. At least one dummy chip consisting of an electrically nonconductive material is arranged on each of the connecting regions that are not populated by power semiconductors.

A semiconductor device of embodiments includes: a die pad; a semiconductor chip fixed on the die pad; and a sealing resin covering the semiconductor chip and at least a part of the die pad. The sealing resin has a first protruding portion provided on one side surface and a second protruding portion provided on another side surface. The cross-sectional area of the first protruding portion is equal to or more than 10% of the maximum cross-sectional area of the sealing resin. The cross-sectional area of the second protruding portion is equal to or more than 10%; of the maximum cross-sectional area. The maximum cross-sectional area is equal to or more than 6 mm.sup.2.

A semiconductor device includes a substrate, a conductive part formed on a front surface of the substrate, a semiconductor chip disposed on the front surface of the substrate, a control unit that controls the semiconductor chip, a sealing resin that covers the semiconductor chip, the control unit and the conductive part, and a first lead bonded to the conductive part and partially exposed from the sealing resin. The conductive part includes a first pad and a second pad disposed apart from each other. The first lead is bonded to the first pad and the second pad.

A semiconductor device is provided, which is configured to improve the adhesion between the resin part and the leads without interfering with proper operation of the semiconductor device. The semiconductor device includes a semiconductor element 1, a first lead 2 including a first pad portion 21, a second lead 3 including a second pad portion 31, a conductor member 61, and a resin part 8. The first pad portion 21 has a first-pad obverse surface 21a including a first smooth region 211 to which an element reverse surface 1b is bonded, and a first rough region 212 spaced apart from the semiconductor element 1 as viewed in z direction and has a higher roughness than the first smooth region 211. The second pad portion 31 has a second-pad obverse surface 31a including a second smooth region 311 to which a second bonding portion 612 is bonded, and a second rough region 312 spaced apart from the second bonding portion 612 as viewed in z direction and has a higher roughness than the second smooth region 311.

A semiconductor device and method is disclosed. In one example, the semiconductor device includes a first diepad including a first mounting surface and a first elevated portion elevated with respect to the first mounting surface. A first semiconductor chip is mounted on the first mounting surface. The semiconductor device further includes a second diepad including a second mounting surface. A second semiconductor chip is mounted on the second mounting surface and includes an electrical contact arranged on a top surface of the second semiconductor chip facing away from the second mounting surface. The semiconductor device further includes a first electrical connection element electrically connecting the electrical contact of the second semiconductor chip and the first elevated portion of the first diepad.

A semiconductor module includes: a substrate; and a semiconductor device that is located on one side of the substrate in a first direction and is conductively bonded to the substrate, wherein the semiconductor device includes: a first terminal, a second terminal, and a third terminal; a semiconductor element that is located on one side of the first terminal, the second terminal, and the third terminal in the first direction; and a sealing resin that covers the semiconductor element, wherein the semiconductor element includes a first circuit and a second circuit that are connected in series with each other, wherein the first circuit is electrically connected to the first terminal and the third terminal, wherein the second circuit is electrically connected to the second terminal and the third terminal, wherein the sealing resin has a bottom surface facing the substrate.