A semiconductor device includes a support member, a semiconductor element and a sealing member. The semiconductor element is disposed on a first side in a thickness direction relative to the support member. The sealing member covers a part of the support member and the semiconductor element. The support member has a first surface facing a second side in the thickness direction and exposed from the sealing member. The first surface is formed with a first uneven region. In an example, the first uneven region has an arithmetic mean roughness between 0.2 m and 13 m. In an example, the first uneven region includes a plurality of uneven lines in an arc shape.

A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.

A semiconductor package includes: a molded body having opposite first and second sides; at least one semiconductor die encapsulated by the molded body; and a die carrier having opposite first and second sides. The semiconductor die is arranged over the first side of the die carrier. The second side of the die carrier is at least partially exposed from the second side of the molded body, forming at least one exposed portion of the die carrier. The first side of the molded body includes a first portion protruding from a second portion in a vertical direction perpendicular to the first side, forming a planar surface. The second portion extends completely along at least one edge of the first side. A center point of the first portion is in vertical alignment with a center point of the exposed portion.

A semiconductor device includes a die carrier, a semiconductor die, a first set of external connectors, and a second set of external connectors. The semiconductor die includes at least a first load electrode and a second load electrode, and is mounted onto the die carrier with the first load electrode being electrically connected to the die carrier. The first set of external connectors is electrically and thermally connected to the die carrier. The second set of external connectors is spaced apart from the die carrier and electrically connected to the second load electrode. An overall wire size of the second set of external connectors is greater than an overall wire size of the first set of external connectors.

A device includes a first conductive-member which connects to a first electrode on a first face of a chip. A second conductive-member is spaced from the chip and the first conductive-member. A third conductive-member is spaced from the first and second conductive-members. A first connector connects between the second electrode and the second conductive-member. A second connector is opposed to a third electrode on the second face and connects the third electrode and the third conductive-member. A first connecting-member connects the first connector and the second face. A second connecting-member connects the first connector and the second conductive-member. The first connector includes first protruded portions protruded in a first direction from the first conductive-member to the second conductive-member. The second connecting-member is provided to correspond to each of places between the first protruded portions and the second conductive-member.

In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.

A stacked transistor arrangement and process of manufacture thereof are provided. Switched electrodes of first and second transistor chips are accessible on opposite sides of the first and second transistor chips. The first and second transistor chips are stacked one on top of the other. Switched electrodes of adjacent sides of the transistor chips are coupled together by a conductive layer positioned between the first and second transistor chips. Switched electrodes on sides of the first transistor chip and the second transistor chip that are opposite the adjacent sides are coupled to a lead frame by bond wires or solder bumps.

A packaged electronic device comprises a power semiconductor die that includes a first terminal and a second terminal, a power substrate comprising a dielectric substrate having a first metal cladding layer on an upper surface thereof, an encapsulation covering the power semiconductor die and at least a portion of the power substrate, a first lead extending through the encapsulation that is electrically connected to the first terminal, and a second lead extending through the encapsulation that is electrically connected to the second terminal. The first terminal is bonded to the first lead via a first transient liquid phase solder joint.

A semiconductor device has a joint part in which a first conducting part and a second conducting part are joined by a joint material. The first conducting part has a high wettability region and a low wettability region in a surface opposite to the second conducting part. The low wettability region is adjacent to the high wettability region to define an outer periphery of the high wettability region and has wettability lower than the high wettability region to the joint material. The high wettability region has an overlap region overlapping a formation region of the joint part in the second conducting part in a planar view, and a non-overlap region connected to the overlap region and not overlapping the formation region of the joint part in the second conducting part. The non-overlap region includes a holding region capable of holding the joint material that is surplus for the joint part.

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.