A power electronics module, having a continuous DBC PCB having power semiconductors arranged on connecting regions of an uppermost layer of said DBC PCB and a lead frame arranged above the power semiconductors for three-dimensional power and control routing, wherein the lead frame has a drain-source connection, which can be brought into electrical contact with a drain-source contact of the PCB, and a load-source connection which is opposite the drain-source connection via the power semiconductors and which is formed from a plurality of subregions, each of which can be brought into electrical contact with one of the power semiconductors, and at least one gate-source terminal and at least one kelvin-source terminal, and a carrier element including an electrically insulating material on which conductor tracks are provided, wherein the carrier element is routed between the power semiconductors in a region between the load-source connection and the drain-source connection.

An electronic device includes: a substrate with obverse and reverse surfaces spaced apart in a thickness direction; an electronic element having an obverse surface formed with a first obverse surface electrode; a wiring portion on the substrate obverse surface and configured to transmit a control signal for the electronic element; a conduction member with obverse and reverse surfaces spaced apart in the thickness direction, where the reverse surface is joined to the wiring portion; a conductive first lead on the substrate obverse surface; and a first connecting member joined to the obverse surface of the conduction member and the first obverse surface electrode. The first lead includes a first pad portion spaced apart from the wiring portion and to which the electronic element is joined. The wiring portion and the first obverse surface electrode are electrically connected to each other via the conduction member and the first connecting member.

According to one embodiment, a semiconductor device includes the following structure. The semiconductor chip is provided between first and second conductors. A joint component is provided between the chip and the second conductor. The thin film is provided on the second conductor and contains a material different from a material of the joint component. The second conductor includes first, second and third plates. The first plate extends in a first direction along a first surface of the chip and is connected to the chip via the joint component. The second plate extends from the first plate obliquely with respect to the first direction. The third plate extends from the second plate in the first direction. The thin film is arranged on a surface of the second plate continuous from a surface on which the joint component is provided.

A package includes a semiconductor die disposed on a lead frame. A source contact pad is disposed on the semiconductor die. The package further includes a lead post shared by a plurality of leads that form external terminals of the package. The lead post has a clip-locking feature. A clip connects the source contact pad to the lead post. The clip has a key structure coupled to the clip-locking feature in the lead post.

A switching power device comprises a device lead-frame. Gates, Kelvin sources and a drain are formed on the device lead-frame, the gates and the Kelvin sources are arranged at one end of the device lead-frame, and the drain is arranged at the other end of the device lead-frame; and two gates and two Kelvin sources are provided. One end of the device lead-frame is sequentially provided with the gate, the Kelvin source, the Kelvin source and the gate, so as to form a symmetrical pin structure.

To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.

A semiconductor package includes: a first transistor chip having opposite first and second sides, the first side including source chip pad(s) (S1) and drain chip pad(s) (D1); a second transistor chip having opposite first and second sides, the first side including source chip pad(s) (S2) and drain chip pad(s) (D2); and a chip carrier having opposite first and second main sides. The first main side of the chip carrier faces the first side of the first transistor chip and is attached to S1 and D1. The second main side of the chip carrier faces the first side of the second transistor chip and is attached to S2 and D2. The chip carrier is configured to electrically connect the transistor chips in a D1-S1-D2-S2, S1-D1-D2-S2 or D1-S1-S2-D2 configuration, and configured to be attached to an application board in an inclined orientation relative to the application board.

A semiconductor device includes: a leadframe having a die pad, first leads and second leads, the second leads being connected with a leadpost; a first lateral transistor die having a first pad, second pad and third pad; a first clip, configured to connect the first pad to the die pad, which is connected with the first leads; and a second clip, configured to connect the second pad to the leadpost of the second leads), the leadpost being disconnected from the die pad. The second clip includes a first section contacting the second pad of the first lateral transistor die, a second section contacting the leadpost of the second leads, and a middle section between the first and the second sections. The middle section has partly a smaller width than the second section.

A semiconductor package and method are disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove and a second groove are formed in the first main surface. The method includes a method of making the semiconductor package.

A chip package structure includes a conductive substrate, a chip, a gate connecting part, a source connecting part, a drain connecting part, a gate conductive wire, a source conductive wire, and a plurality of pins. The gate connecting part is located at a side of the chip. The source connecting part is located at the side of the chip and is separated from the gate connecting part. The source conductive wire is connected to a source electrode of the chip and the source connecting part. The pins include a first pin, a second pin, and one or more third pins. The first pin is connected to the gate connecting part. The second pin is connected to the one or more third pins by the source connecting part.