H10W70/042

Method of manufacturing semiconductor devices, corresponding substrate and semiconductor device
12557669 · 2026-02-17 · ·

Semiconductor chips to be singulated to individual semiconductor devices are arranged onto respective adjacent areas of a mounting substrate such as a pre-molded leadframe. The mounting substrate is made of a laminar, electrically conductive sculptured structure with molded electrically insulating material. Electrically conductive side formations in the adjacent areas of the mounting substrate include first and second pads at front and back surfaces, respectively, of the mounting substrate. The first contact pads at the front surface of the substrate include narrowed portions having side recesses. The second contact pads at the back surface of the substrate include widened portions having side extensions adjacent the side recesses. The electrically insulating material extends into the side recesses to provide anchoring formations of the insulating material to the electrically conductive sculptured structure of the mounting substrate.

INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME HAVING CENTRAL OPENING FILLED WITH A DROP-IN DIE PAD

An integrated circuit package includes a leadframe with leads delimiting a center cavity. The leads of the leadframe have upper surfaces with a surface texture or finish having a first surface roughness. A drop-in die pad is installed within the center cavity. The drop-in die pad has an upper surface with a surface texture or finish having a second surface roughness that is rougher than the first surface roughness. An integrated circuit die is mounted to the upper surface of the drop-in die pad and electrical connections are formed between bonding pads of the integrated circuit die and the leads of the leadframe. An encapsulation body encapsulates the leadframe, drop-in die pad and electrical connections.

Flip chip bonding for semiconductor packages using metal strip

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

Universal Surface-Mount Semiconductor Package

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
20260090400 · 2026-03-26 ·

According to one embodiment, a semiconductor device includes first and second frames, a first semiconductor chip, a wire, and a resin. The second frame is arranged so as to face the first frame in a first direction, and has a stepped portion on an end portion of an upper surface. The first semiconductor chip is arranged on a bottom surface of the stepped portion. The wire electrically couples the first semiconductor chip and the first frame. The resin covers part of each of the first and second frames and seals the first semiconductor chip and the wire. A lower surface of the first frame and a side surface of the first frame in the first direction are exposed from the resin. A lower surface of the second frame and a side surface of the second frame in the first direction are exposed from the resin.

Integrated circuit in hybrid row height structure

An integrated circuit includes a first cell and a second cell. The first cell has a first height along a first direction. The second cell has a second height shorter than the first height along the first direction. A transistor of the first cell and a transistor of the second cell share a first active area, and a first boundary of the first cell, a first boundary of the second cell, a second boundary of the first cell and a second boundary of the second cell are arranged in order along the first direction.