A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; and an insulating layer. The gate electrode includes a junction portion and a drain-side protruding portion. The insulating layer includes an in-situ Si.sub.3N.sub.4 film and an ex-situ Si.sub.3N.sub.4 film. At least one of the following is satisfied: (a) the halogen concentration of the in-situ Si.sub.3N.sub.4 film is lower than the halogen concentration of the ex-situ Si.sub.3N.sub.4 film; or (b) the interface oxygen concentration between the in-situ Si.sub.3N.sub.4 film and the nitride semiconductor layer is lower than the interface oxygen concentration between the ex-situ Si.sub.3N.sub.4 film and the in-situ Si.sub.3N.sub.4 film.

A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; a drain-side insulating layer; and a source-side insulating layer. The gate electrode includes a junction portion, a drain-side protruding portion, and a source-side protruding portion. The protrusion length of the source-side protruding portion is longer than the protrusion length of the drain-side protruding portion. The bottom surface of the source-side protruding portion includes a step. The height of an end portion of the bottom surface of the source-side protruding portion is greater than the height of an end portion of the bottom surface of the drain-side protruding portion.

A chip package unit, a method of manufacturing the same, and package structure formed by stacking the same are provided. At least one first connecting pad, at least one second connecting pad, and at least one third connecting pad of a flexible printed circuit (FPC) board in the chip package unit are electrically connected with one another by circuit of the FPC board. At least one die pad disposed on a front surface of a chip is electrically connected with the first connecting pad first and then electrically connected with the outside by the second connecting pad or the third connecting pad. Thereby the chip of the chip package unit can be electrically connected with the outside by the front surface or a back surface thereof. Therefore, not only production is reduced due to simplified production process and energy saved, volume of the package structure is also reduced.

A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region. The edge termination region includes one or more guard rings in the drift region. The drift region has a first conductivity type and the one or more guard rings have a second conductivity type. The edge termination region may also include a passivation layer that is disposed on the one or more guard rings and on the drift region in the edge termination region. The passivation layer has a first thickness over each guard ring and a second thickness over the drift region, where the first thickness is greater than the second thickness. Alternatively, the edge termination region may also include a passivation layer that is only disposed on the one or more guard rings in the edge termination region.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first member. The second electrode includes first and second electrode regions. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial region. The second semiconductor region includes first to third semiconductor portions. At least a part of the third semiconductor portion is between the first semiconductor region and the second electrode region. The second semiconductor portion is between the first semiconductor portion and the third semiconductor region. The first member includes first and second regions.

Semiconductor devices including dual surface passivation layers are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, a drain access region, and a source access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate electrode is disposed in the gate region of the semiconductor substrate, where the gate electrode includes an asymmetrical source-side field plate (e.g., including a single-step profile) extending over at least a portion of the source access region of the semiconductor substrate.

A transistor device includes a semiconductor structure, a multi-layer passivation stack on the semiconductor structure, source and drain contacts on the semiconductor structure, and a gate on the semiconductor structure between the source and drain contacts. The multi-layer passivation stack includes a plurality of passivation layers having different electrical properties, and at least one opening extending through the passivation layers. The at least one opening exposes a surface of the semiconductor structure between the gate and the source or drain contact.

A high electron mobility transistor includes a substrate, a barrier layer, a semiconductor layer and an insertion layer. The barrier layer is disposed on the substrate and includes aluminum gallium indium nitride. The semiconductor layer is disposed between the substrate and the barrier layer. The insertion layer is disposed between the semiconductor layer and the barrier layer, and includes aluminum gallium nitride.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.