A lateral Schottky barrier diode includes a single crystal AlN substrate, an unintentionally doped AlN layer, a silicon-doped AlN layer, an unintentionally doped GaN layer, a passivation layer, a plurality of ohmic contacts, and a Schottky contact.

A nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a gate dielectric layer, and a gate electrode. The second III-V nitride-based semiconductor layer is disposed over the first III-V nitride-based semiconductor layer and has a bandgap higher than a bandgap of the first III-V nitride-based semiconductor layer. The gate dielectric layer is disposed over the second III-V nitride-based semiconductor layer. The gate electrode is disposed over the gate dielectric layer and includes a first portion and a first portion. The first portion makes contact with the gate dielectric layer and has a rounded corner.

A method of producing a power semiconductor device includes: providing a semiconductor body with a front side having a substantially horizontal area above both an active region and an edge termination region of the semiconductor body; forming, at the front side, a first insulation layer above both the active region and the edge termination region; forming, at the first insulation layer, a first mask layer that covers the edge termination region at least partially and exposes the active region; removing a portion of the first insulation layer covering the active region; and while the first mask layer or a modified first mask layer or another mask layer covers the edge termination region, subjecting the edge termination region to a first implantation processing step to form, in the edge termination region, one or more doped semiconductor regions.

Semiconductor devices including one or more interfacing segments patterned within an outer protective layer and associated systems and methods are disclosed herein. The one or more interfacing segments may provide attachment interfaces/surfaces for connection pads. The one or more interfacing segments or a portion thereof may remain uncovered or exposed and provide warpage control for the corresponding semiconductor device.

A device structure may be provided by: forming semiconductor devices and metal interconnect structures formed within dielectric material layers over a semiconductor substrate; forming metal pads in a topmost layer of the dielectric material layers; forming a passivation layer stack including a first dielectric diffusion barrier layer, a silicate glass layer, a second dielectric diffusion barrier layer, and a polymer layer; forming openings through the passivation layer stack over the metal pads; forming die bump structures on the metal pads; and dicing a wafer including the passivation layer stack, the dielectric material layers, and the semiconductor substrate along dicing channels into a plurality of semiconductor dies.

A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

A chip-size-package type semiconductor device includes a semiconductor layer, pads, and metal redistributions that are located above a top surface of the semiconductor layer and each of which is connected to one or more pads. The metal redistributions include first metal redistributions each of which includes a first portion and a second portion contained within the first portion in a plan view, the second portion being located above the first portion and having an area smaller than an area of the first portion in the plan view. Each of the first metal redistributions includes one or more line-shaped bends in a boundary portion between the first portion and the second portion on a surface of the first metal redistribution, the one or more line-shaped bends each having an interior angle of at least 180 degrees in a cross section of the first metal redistribution.

A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.

Various embodiments pertain to a high mobility transistor element resulting from IGTO oxide semiconductor crystallization, and a production method for same, the transistor element comprising a substrate and a crystalline IGTO channel layer disposed on the substrate, and being produced by converting a non-crystalline IGTO channel layer provided on the substrate to a crystalline IGTO channel layer.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.