The present description concerns a method of manufacturing an ultrasonic device comprising an electronic circuit and an electroacoustic component, the method comprising the forming of first connection pads bonded to a plate comprising one electroacoustic component or a plurality thereof, the forming of solder balls on the first pads, the melting of the solder balls so that they adhere to the first pads, optionally the cutting of the plate to separate the electroacoustic components, the forming of second connection pads bonded to the electronic circuit, the application of the electroacoustic component to the electronic circuit so that the solder balls come into contact with the second pads, and the melting of the solder balls so that they adhere to the first pads and to the second pads.

An electronic package is provided, in which an electronic element is disposed on a carrier structure, and an interposer is stacked on the electronic element. Further, a wire is connected to the interposer and grounds the carrier structure, such that the wire and the interposer surround the electronic element. Therefore, the wire can be used as a shielding element when the electronic package is in operation to prevent the electronic element from being subjected to external electromagnetic interference.

A semiconductor device includes a semiconductor element having a surface on which a first electrode and a second electrode are disposed, a conductor plate having a surface facing the surface of the semiconductor element and electrically connected to the first electrode, an insulating layer disposed on the surface of the conductor plate and covers a part of the surface of the conductor plate, and a conductor circuit pattern disposed on the insulating layer. The conductor circuit pattern has at least one conductor line electrically connected to the semiconductor element. The at least one conductor line includes a conductor line electrically connected to the second electrode.

A stacked package structure and a forming method thereof are disclosed. The forming method includes mounting a first active surface of a first chip facing down on an upper surface of a substrate; forming a chip stacking structure on a first back surface of the first chip, including a plurality of second chips stacked sequentially in a vertical direction; performing a mass reflow process to solder the micro bumps of the upper second chip to the second connection terminals of the adjacent lower second chip; and performing a molded underfill process to form a molding layer filled between the upper and lower second chips and between the lower second chip and the first chip. This improves packaging efficiency, prevents the micro bumps from collapsing, and ensures evenness during stacking.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

A semiconductor device, including: a semiconductor chip having a plurality of main electrodes and a gate electrode; a first substrate on which the semiconductor chip is mounted; a second substrate located above the first substrate, the second substrate having a conductive plate on a front surface thereof, the conductive plate being electrically connected to the semiconductor chip; and a case having an opening in an upper surface thereof, at least a part of the conductive plate being exposed through the opening, the case incorporating the semiconductor chip, the first substrate, and the second substrate.

A method for making semiconductor package, wherein the method comprises: providing a substrate and a plurality of semiconductor dice; forming an integrated interposer block comprising a first interposer layer, a second interposer layer and a dummy portion, wherein the integrated interposer block defines a central axis, wherein the first interposer layer and the second interposer layer are symmetric with respect to the central axis to form an interposer pyramid; removing the dummy portion from the integrated interposer block to form a pair of step structures, wherein each step structure comprises two step surfaces; attaching the interposer pyramid on the substrate; attaching a first pair of semiconductor dice on the substrate; attaching a second pair of semiconductor dice on the first interposer layer and the first pair of semiconductor dice; and forming an encapsulant layer on the substrate to encapsulate the interposer pyramid and the semiconductor dice.

A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least 100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.

A semiconductor processing apparatus includes a process chamber that defines an enclosure. The enclosure includes a substrate support configured to support a substrate and rotate the substrate about a central axis of the process chamber. The substrate support is also configured to move vertically along the central axis and position the substrate at multiple locations in the enclosure. The apparatus also includes one or more UV lamps configured to irradiate a top surface of the substrate supported on the substrate support.

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.