Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

The semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, a transistor, and a through-silicon-via (TSV) structure. The transistor is over the substrate. The TSV structure penetrates the substrate and comprises a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is between the first conductive layer and the second conductive layer. The method of manufacturing the same includes the following steps: forming a via hole in a substrate; forming a first conductive layer in the via hole; forming a dielectric layer in the via hole and over the first conductive layer; forming a second conductive layer in the via hole and over the dielectric layer; and forming a transistor over the substrate. The first conductive layer, the dielectric layer, and the second conductive layer collectively form a through-silicon-via (TSV) structure.

Provided is a semiconductor package including a first semiconductor chip; a plurality of lower first conductive posts on the first semiconductor chip; a second semiconductor chip offset-stacked on the first semiconductor chip; a plurality of lower second conductive posts on the second semiconductor chip; a first molding layer around the first semiconductor chip, and the second semiconductor chip; a third adhesive layer on an upper surface of the first molding layer; a plurality of upper first conductive posts on the plurality of lower first conductive posts; a plurality of upper second conductive posts on the plurality of lower second conductive posts; a third semiconductor chip on the third adhesive layer; a plurality of third conductive posts on the third semiconductor chip; a second molding layer on the third adhesive layer; and a redistribution structure on the second molding layer.

A semiconductor chip may include: a semiconductor substrate; a through silicon via that vertically penetrates the semiconductor substrate; an integrated device layer on a first surface of the semiconductor substrate and including integrated devices; a multi-wiring layer on the integrated device layer and including layers of wires; an upper metal layer on the multi-wiring layer and connected to the wires; and a lower metal layer on a second surface of the semiconductor substrate. The semiconductor substrate may include a lower bump area on the second surface of the semiconductor substrate, the lower bump area including bump pads thereon, and the lower metal layer may be on a periphery of the lower bump area.

A semiconductor package may include a substrate including a plurality of vias and a chip stack on the substrate. The chip stack may include a plurality of semiconductor chips, wherein a first semiconductor chip is a lowermost one of the plurality of semiconductor chips in the chip stack, chip pads of the first semiconductor and substrate pads of the substrate are bonded to each other, and the chip pads and the substrate pads are integrally formed of the same metal material, the first semiconductor chip includes a corner region adjacent to a corner of the first semiconductor chip, and a center region excluding the corner region, the substrate includes a trench on an upper surface of the substrate, and the trench extends along a boundary between the corner region and the center region of the first semiconductor chip.

A semiconductor device includes a wiring substrate having an upper surface, a semiconductor chip mounted on the wiring substrate, and a stiffener ring fixed onto the wiring substrate via a plurality of adhesive layers. The upper surface is a quadrangular shape, and first and second center lines and first and second diagonal lines can be drawn. The stiffener ring has four extension portions and four corner portions. Adhesive layers include first, second, third and fourth adhesive layers that respectively overlap with the four extension portions and that are arranged at a portion overlapping with one of the first center line and the second center line. Also the adhesive layers include fifth, sixth, seventh, and eighth adhesive layers that respectively overlap with the four corner portions and that are arranged at a portion overlapping with one of the first diagonal line and the second diagonal line.

The semiconductor package includes a lower package including a lower package substrate and a lower semiconductor device disposed on the lower package substrate, and an upper package including an upper package substrate disposed on the lower package in a first direction and an upper semiconductor device disposed on the upper package substrate, and the upper package substrate includes a wiring structure on which the upper semiconductor device is mounted, and a heat sink disposed so that at least a portion overlaps the wiring structure in at least one of the first direction and a second direction perpendicular to the first direction and including a heat radiation pattern, wherein the heat radiation pattern comprises an insulator and a heat radiator in a repeated alternating pattern and wherein the lower semiconductor device overlaps at least a portion of the wiring structure and the portion of the heat sink in the first direction.

A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

Provided is a redistribution structure having reduced parasitic capacitance. The redistribution structure may include a via layer and a wiring layer disposed on the via layer in a first direction perpendicular to the via layer, the wiring layer including a metal plate and a first insulation pattern configured to penetrate the metal plate in the first direction. An outer side surface of the first insulation pattern may be exposed from a side surface of the metal plate.