The present disclosure relates to a flip-chip based moisture-resistant module, which includes a substrate with a top surface, a flip-chip die, a sheet-mold film, and a barrier layer. The flip-chip die has a die body and a number of interconnects, each of which extends outward from a bottom surface of the die body and is attached to the top surface of the substrate. The sheet-mold film directly encapsulates sides of the die body, extends towards the top surface of the substrate, and directly adheres to the top surface of the substrate, such that an air-cavity with a perimeter defined by the sheet-mold film is formed between the bottom surface of the die body and the top surface of the substrate. The barrier layer is formed directly over the sheet-mold film, fully covers the sides of the die body, and extends horizontally beyond the flip-chip die.

A semiconductor device has a substrate and an electrical component disposed over the substrate. A heat spreader with a plasma-enhanced surface is disposed over the electrical component. A TIM is disposed between the electrical component and plasma-enhanced surface of the heat spreader. The TIM can be deposited on the electrical component or plasma-enhanced surface. The plasma-enhanced surface contains argon ions and oxygen ions. The heat spreader is disposed in a reaction chamber. Reactant gases, such as argon and oxygen, are introduced into the reaction chamber. An electric field is formed within the reaction chamber to ionize the argon and oxygen and form the plasma-enhanced surface. The plasma-enhanced surface has properties of roughness and tacky-ness or adhesive property by nature of the surface exhibiting a chemical bonding group. An underfill material is deposited between the electrical component and substrate. The electrical component can be a flipchip type semiconductor die.

System-in-packages (SiPs) having vertically integrated processing units and combined high-bandwidth memory (HBM) devices, and associated devices and methods, are disclosed herein. In some embodiments, the SiP includes a processing unit and a HBM device carried by the processing unit. Further, the combined HBM device can include one or more volatile memory dies and one or more non-volatile memory dies. The SiP can also include a shared through silicon via (TSV) bus that electrically couples combined HBM device can also include a shared bus that is electrically coupled to each of the processing unit, the one or more volatile memory dies, and the one or more non-volatile memory dies to establish communication paths therebetween.

A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.

A light-emitting device includes a carrier substrate, a flip-chip light-emitting diode (LED) mounted onto the carrier substrate, and an electrode unit disposed between the carrier substrate and the flip-chip LED. The electrode unit includes first and second connecting electrodes that have opposite conductivity. Each of the first and second connecting electrodes includes an intermediate metal layer and a binding layer that are sequentially disposed on the flip-chip LED in such order. The binding layer includes a first portion being adjacent to the carrier substrate and forming an eutectic system with tin, and a second portion located between the first portion and the intermediate metal layer.

A method of fabricating an electronic device including fabricating a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and fabricating a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

Disclosed herein is a multi-die device, and an integrated chip package assembly having the multi-die device. The multi-die device includes a first IC die and a second IC die disposed at a same tier; a first conductive pillar coupled with the first IC die; a second conductive pillar coupled with the second IC die; and an interconnecting die disposed between the first conductive pillar and the second conductive pillar and configured to couple with the first IC die and the second IC die. The multi-die device further includes a first interconnecting interface disposed on the first IC die; a second interconnecting interface disposed on the second IC die, the first interconnecting interface and the second interconnecting interface being separated by a molding material.

A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.

A semiconductor device has a substrate. A first electrical component and second electrical component are disposed over the substrate. A zero-ohm resistor is disposed over the substrate between the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and first zero-ohm resistor. An opening is formed through the encapsulant to the first zero-ohm resistor. A shielding layer is formed over the encapsulant and into the opening.