A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

A component forming machine with jammed component mitigation. In some examples, the component forming machine can include a platform configured to receive a lower die that supports a plurality of components for forming and includes a void through which at least some of the plurality of components pass subsequent to the forming, a die press positioned above the lower die and configured to lower an upper die to exert downward pressure on the plurality of components to form unformed components and formed components, and a separation system. In some examples, the separation system is configured to interact with the lower die to permit the formed components to fall into the void and prevent the unformed components from falling into the void.

Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

The present disclosure is directed to semiconductor packages manufactured utilizing a leadframe with varying thicknesses. The leadframe with varying thicknesses has a reduced likelihood of deformation while being handled during the manufacturing of the semiconductor packages as well as when being handled during a shipping process. The method of manufacturing is not required to utilize a leadframe tape based on the leadframe with varying thicknesses. This reduces the overall manufacturing costs of the semiconductor packages due to the reduced materials and steps in manufacturing the semiconductor packages as compared to a method that utilizes a leadframe tape to support a leadframe. The semiconductor packages may include leads of varying thicknesses formed by utilizing the leadframe of varying thicknesses to manufacture the semiconductor packages.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a first semiconductor die, a second semiconductor die on the first semiconductor die, an underfill layer between the first semiconductor die and the second semiconductor die, and a mold layer on a top surface of the first semiconductor die and a lateral surface of the second semiconductor die. The first semiconductor die includes a first semiconductor substrate and an edge conductive pad on a rear surface of the first semiconductor substrate. One portion of the edge conductive pad overlaps the second semiconductor die. Another portion of the edge conductive pad is covered with the mold layer.

A method of forming a semiconductor package includes forming, on a first semiconductor chip, a plurality of inner connection terminals and a preliminary underfill covering the plurality of inner connection terminals, stacking the first semiconductor chip on a lower structure such that the preliminary underfill is bonded between the first semiconductor chip and the lower structure, and curing the preliminary underfill using a laser bonding process, thereby forming a first underfill, and reflowing the plurality of inner connection terminals during a formation of the first underfill through the curing of the preliminary underfill.