An electronic device includes: a first substrate; an element layer disposed on the first substrate and including an active area and a peripheral area surrounding the active area; a first bonding pad disposed on the peripheral area of the element layer; a second substrate disposed opposite to the first substrate; a second bonding pad disposed on the second substrate and including a first part and a second part surrounding the first part; and a bonding material disposed between the first part of the second bonding pad and the first bonding pad and between the second part of the second bonding pad and the first bonding pad.

Bonded die structures and methods of fabricating bonded die structures including improved positioning of the dies used to form the structures. Improved positioning may be achieved by providing non-linear alignment features around the periphery of the dies that may facilitate accurate positioning of the dies with respect to one or more alignment marks on the target structures on which the dies are placed. The non-linear alignment features may include features formed in the peripheral edges of the dies, such as indent portions extending inwardly from the peripheral edges of the dies and/or outward bulge portions extending outwardly from the peripheral edges of the dies. Alternatively, or in addition, the non-linear alignment features may be features formed in a seal ring structure of the dies. The non-linear alignment features may improve the accuracy of the positioning of the dies relative to alignment mark(s) on the target structures using optical detection systems.

A method is provided, including forming a wafer structure including a sacrificial layer between first and second substrates; forming first sacrificial structures within the second substrate in the spacing regions; forming second sacrificial structure within the second substrate; forming conductive vias through the second substrate in the die regions; forming dielectric layers over the second substrate and forming conductive features in the dielectric layers in the die regions; forming first windows through the dielectric layers and extending to the first sacrificial structures; forming second window through the dielectric layers and extending to the second sacrificial structure; forming a protective layer over the dielectric layers and filling the first windows; attaching a carrier substrate to the protective layer; removing the sacrificial layer, first sacrificial structures, and second sacrificial structure by flowing an etchant through the at least one second window; removing the protective layer; and detaching the carrier substrate.

A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a packaging substrate having a plurality of grooves orthogonally arranged and substantially surrounding a plurality of package sites. A plurality of semiconductor die is affixed on a first major side of the packaging substrate. Each semiconductor die of the plurality of semiconductor die is affixed at a unique package site of the plurality of package sites. An encapsulant encapsulates the first major side of the packaging substrate such that each semiconductor die of the plurality of semiconductor die is encapsulated by the encapsulant. A singulation cut is formed along each groove of the plurality of grooves of the packaging substrate to form individual semiconductor device units.

A mask member, a light emitting element transfer device, and a transfer method are provided. A mask member includes a first mask including a light blocking pattern layer and a base layer, wherein the light blocking pattern layer of the first mask includes a plurality of opening patterns, and a second mask including a light blocking pattern layer and a base layer, wherein the light blocking pattern layer of the second mask includes a plurality of opening patterns disposed at angles relative to a center of the second mask. The mask member defining a transfer area by overlapping an opening pattern of the plurality of opening patterns of the first mask and an opening pattern of the plurality of opening patterns of the second mask.

A mask-to-donor alignment method for laser-induced forward transfer includes (a) directing a laser beam onto a mask to produce a masked beam including one or more separate sub-beams, each sub-beam being transmitted by a respective aperture of the mask, (b) viewing each sub-beam, as transmitted by a donor substrate carrying one or more devices, to obtain imagery indicating in each sub-beam a shadow of a corresponding one of the one or more devices, and (c) based on the imagery, adjusting position of the masked beam and the donor substrate, relative to each other, so as to align each device with respect to the corresponding sub-beam. This in-situ observation of the relative alignment between the donor substrate and the masked beam produces an improved alignment accuracy, as compared to the indirect fiducial-based alignment method. Alignment accuracies better than 0.2 m, and associated sub-1 m LIFT positioning accuracies, have been demonstrated.

The present disclosure as an embodiment provides a semiconductor package including a first redistribution structure; conductive bumps arranged on a lower surface of the first redistribution structure; a semiconductor chip arranged on an upper surface of the first redistribution structure; an encapsulant that encapsulates at least a portion of the semiconductor chip; a second redistribution structure disposed on the encapsulant and including an insulating layer and a first wiring layer including a first conductive pattern exposed to a side surface of the insulating layer; and a conductive post that penetrates the encapsulant to electrically connect the first redistribution structure and the second redistribution structure.

Electronic packages, die structures and methods of fabrication are described in which a recess is formed by removing material from the edges and corners of a die that may increase the risk of non-bonding or delamination. In an embodiment, a die includes a recess with a width that extends from a perimeter edge to a recessed edge, and a depth that extends from a top surface to a recess floor. In some embodiments, the recess is filled with gap fill material. In other embodiments, the recess is not filled with gap fill material.

Implementations of a substrate may include a first set of tie bars; a second set of tie bars; and a plurality of leads coupled between the first set of tie bars and the second set of tie bars. The first set of tie bars may intersect with the second set of tie bars. Each intersection of the first set of tie bars and the second set of tie bars may be downset from the plurality of leads.

A semiconductor package having one or more bifacial NAND memory devices includes an interposer including a plurality of multiplexers (MUX) integrally formed within the interposer, and a plurality of bifacial NAND memory devices disposed over the interposer. The bifacial NAND memory devices are electrically coupled to the MUX. Each bifacial NAND memory device includes a first NAND memory die disposed on a first planar surface, and a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, and adjacent the interposer. Each bifacial NAND memory device also includes a plurality of through silicon vias (TSVs) electrically coupling the first NAND memory die with the second NAND memory die, and the MUX.