Disclosed herein is a method for manufacturing a semiconductor comprising mechanically connecting one or more separate semiconductor components to a common intermediate carrier, arranging the intermediate carrier with respect to a substrate so that, at least for a majority of the semiconductor components, at least one solder pad of a particular semiconductor component lies opposite a solder pad of the substrate associated therewith forming a solder joint, and connecting mutually associated solder pads of the one or more semiconductor components and the substrate by melting and solidifying a solder material arranged between the mutually associated solder pads. A surface tension of the solder material between the mutually associated solder pads of the substrate and the one or more semiconductor components sets a predetermined position of the intermediate carrier relative to the substrate, in which the one or more semiconductor components assume a target position relative to the substrate.

A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

A Pluggable Multipurpose Module (PMM)/Data Center-Modular Hardware System Host Processor Module (DC-MHS HPM) interposer includes an interposer board having a DC-MHS HPM connector subsystem that connects to a DC-MHS HPM, and a PMM connector subsystem that connects to a computing device. An interposer Baseboard Management Controller (BMC) on the interposer board is coupled to the DC-MHS HPM connector subsystem and configured to perform management operations on a DC-MHS HPM connected to the DC-MHS HPM connector subsystem. A power controller on the interposer board is coupled to the PMM connector subsystem and configured to be cabled to a DC-MHS HPM connected to the DC-MHS HPM connector subsystem. A translation subsystem on the interposer board is coupled to the DC-MHS HPM connector subsystem and the PMM connector subsystem and configured to perform PMM/DC-MHS HPM translations on data transmitted between the DC-MHS HPM connector subsystem and the PMM connector subsystem.

A semiconductor storage device according to an embodiment includes a board, a first semiconductor memory, a second semiconductor memory, a controller, and a wiring. The first semiconductor memory includes a first bonding member. The first semiconductor memory has a first corner, a second corner, a third corner, and a fourth corner. The second semiconductor memory includes a second bonding member. The second semiconductor memory has a fifth corner, a sixth corner, a seventh corner, and an eighth corner. The first bonding member is a first detection-bonding member. The first detection-bonding member detects a connection state of the first semiconductor memory and the second semiconductor memory. The second bonding member is a second detection-bonding member. The second detection-bonding member is electrically connected to the first detection-bonding member. The second detection-bonding member detects a connection state of the first semiconductor memory and the second semiconductor memory.

A microelectronic device comprises: a die; a first metal column over a first bond pad of the die; a first metal strip over the die; a second metal column over the first metal strip; and a second metal strip over the first and second metal columns and over the die, in which the second metal strip has a pair of bent segments and a first segment coupled between the pair of bent segments.

A semiconductor chip having at least two electrical contact points which are arranged on a main surface of the semiconductor chip is disclosed, a metallic reservoir layer being applied over the entire surface over or on the electrical contact point. A diffusion barrier layer is applied in direct contact on the metallic reservoir layer, the diffusion barrier layer being arranged offset with respect to the metallic reservoir layer, so that the metallic reservoir layer is partially freely accessible. In this case, the diffusion barrier layer forms an adhesion surface for a solder and/or a first solder component of the solder and/or a second solder component of the solder. Methods for connecting a semiconductor chip to a connection carrier are also given.

A Pluggable Multipurpose Module (PMM)/Data Center-Modular Hardware System Host Processor Module (DC-MHS HPM) interposer includes an interposer board having a DC-MHS HPM connector subsystem that connects to a DC-MHS HPM, and a PMM connector subsystem that connects to a computing device. An interposer Baseboard Management Controller (BMC) on the interposer board is coupled to the DC-MHS HPM connector subsystem and configured to perform management operations on a DC-MHS HPM connected to the DC-MHS HPM connector subsystem. A power controller on the interposer board is coupled to the PMM connector subsystem and configured to be cabled to a DC-MHS HPM connected to the DC-MHS HPM connector subsystem. A translation subsystem on the interposer board is coupled to the DC-MHS HPM connector subsystem and the PMM connector subsystem and configured to perform PMM/DC-MHS HPM translations on data transmitted between the DC-MHS HPM connector subsystem and the PMM connector subsystem.

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.