A semiconductor device includes: a semiconductor element; and a first conductor and a second conductor respectively joined to a first surface and a second surface of the semiconductor element via Sn-based solder, in which a Ni-based plated layer is formed on surfaces of the first conductor and the second conductor that oppose the Sn-based solder and on the first surface and the second surface of the semiconductor element, and an interface reaction inhibition layer made of (Cu, Ni).sub.6Sn.sub.5 and having a layer thickness of 1.2 to 4.0 m is formed at an interface between the Ni-based plated layer and the Sn-based solder.

In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

A structure includes an Sn layer or an Sn alloy layer formed above a substrate, and an under barrier metal formed between the substrate and the Sn layer or Sn alloy layer. The under barrier metal is an Ni alloy layer containing Ni, and at least one selected from W, Ir, Pt, Au, and Bi, and can sufficiently inhibit generation of an intermetallic compound through a reaction, caused due to metal diffusion of a metal contained in the substrate, between the metal and Sn contained in the Sn layer or Sn alloy layer.

The semiconductor structure includes a die structure including: a substrate, a first dielectric disposed over the substrate, a first interconnect structure disposed within the first dielectric, a second dielectric disposed on the first dielectric, and a conductive pad surrounded by the second dielectric; a capping member surrounding the die structure; and an insulating member surrounding the capping member, wherein the capping member includes a first oxynitride layer in contact with the die structure or the insulating member.

Disclosed herein are methods of forming a microelectronic component. In some embodiments, the method includes providing an element having a metallization layer that comprises a field dielectric and a conductive feature embedded in the field dielectric. The metallization layer also comprises a surface that includes the field dielectric and the conductive feature. The method further includes forming a copper feature over the conductive feature, forming a dielectric layer over sidewalls of the copper feature, and then planarizing the dielectric layer to form a hybrid bonding surface, where the copper feature is exposed at the hybrid bonding surface.

A method for forming a semiconductor structure for wafer level bonding includes the steps of forming a bonding dielectric layer on a substrate, forming an opening in the bonding dielectric layer, wherein an bottom angle between a sidewall and a bottom surface of the opening is smaller than 90 degrees, forming a conductive material layer on the bonding dielectric layer and filling the opening, and performing a chemical mechanical polishing process to remove the conductive material layer outside the opening, thereby forming a bonding pad in the opening.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A method of manufacturing a semiconductor package may include: preparing a semiconductor wafer including rear pads and a rear insulating layer surrounding the rear pads, the rear insulating layer including first recesses spaced apart from the rear pads in a first lateral direction; preparing second semiconductor chips including front pads and a front insulating layer surrounding the front pads, the front insulating layer including second recesses spaced apart from the front pads in the first lateral direction; forming an air gap between the first recesses and the second recesses in a vertical direction by disposing the second semiconductor chips on the semiconductor wafer, the rear pads contacting the front pads; and bonding the rear insulating layer and the front insulating layer to each other and bonding the rear pads and the front pads to each other by performing a thermal compression process.

A light-emitting device includes a substrate and an epitaxial unit. The substrate has a first and a second surface. The substrate is formed on the first surface with a plurality of protrusions. The epitaxial unit includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially disposed on the first surface of the substrate. The first surface of the substrate has a first area that is not covered by the epitaxial unit, and a second area this is covered by the epitaxial unit. A height difference (h2) between the first area and the second area is no greater than 1 m. A display apparatus and a lighting apparatus are also disclosed.