In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

A display device according to the present invention, includes: a first substrate including a first single-crystal semiconductor substrate provided with a plurality of light emitting portions and with a first drive circuit that drives the plurality of light emitting portions, wherein the first single-crystal semiconductor substrate includes a plurality of light guiding portions that transmit light so as to implement a see-through function.

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

A method for forming a semiconductor package structure includes following operations. A first semiconductor wafer is received. The first semiconductor wafer includes a first front side and a first backside. The first semiconductor wafer has a first central region and a first peripheral region. The first semiconductor wafer includes a first interconnect structure in the first central region on the first front side, a first ring structure in the first peripheral region on the first front side, and a first bonding layer over the first ring structure and the first interconnect structure on the first front side. A second semiconductor wafer is received. The second semiconductor wafer has a second front side and a second backside. The second semiconductor wafer includes a second bonding layer disposed on the second front side. The first bonding layer is bonded to the second bonding layer.

An inspection pattern capable of performing wafer-level automatic inspection using a cantilever-type probe card is provided. An inspection pattern according to one embodiment of the present disclosure includes: a Cu pillar pad formed on a semiconductor substrate; a Cu pillar formed on the Cu pillar pad; and an inspection pad formed on the semiconductor substrate, electrically coupled adjacent to or proximate to the Cu pillar pad, and configured to provide a region that a cantilever-type probe comes in contact with during wafer-level automatic inspection.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. A semiconductor structure includes a first chip. The first chip includes a first interconnect layer, a first conductive layer disposed on the first interconnect layer, a first dielectric layer covering the first conductive layer, and a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer. The method of manufacturing the semiconductor structure includes the following operations. A first conductive layer is formed on a first interconnect layer. A first dielectric layer is formed on the first conductive layer and the first interconnect layer. The first dielectric layer is etched to form a first trench on the first conductive layer. A portion of the first conductive layer is etched to form a second trench. A first bonding pad is formed in the second trench.

A semiconductor package may include a base chip, at least one chip stack module on the base chip, and a sealant on the base chip and sealing the at least one chip stack module. The at least one chip stack module may have an integral structure, in which a plurality of memory chips may be stacked and uniform. Each chip stack module of the at least one chip stack module may be on the base chip while having the integral structure.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.